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检索条件"任意字段=7th International Conference on Algorithms and Architectures for Parallel Processing"

共 2981 条记录，以下是341-350 订阅

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Massively parallel Path Space Filtering 14th

Massively Parallel Path Space Filtering

引用

14th international conference on Monte Carlo and Quasi-Monte Carlo Methods in Scientific Computing (MCQMC)

作者： Binder, Nikolaus Fricke, Sascha Keller, Alexander NVIDIA Fasanenstr 81 D-10623 Berlin Germany Tech Univ Carolo Wilhelmina Braunschweig D-38106 Braunschweig Germany

ISBN: (纸本)9783030983192;9783030983185

Restricting path tracing to a small number of paths per pixel in order to render images faster rarely achieves a satisfactory image quality for scenes of interest. However, path space filtering may dramatically improve the visual quality by sharing information across vertices of paths classified as proximate. Unlike screen space approaches, these paths neither need to be present on the screen, nor is filtering restricted to the first intersection with the scene. While searching proximate vertices had been more expensive than filtering in screen space, we greatly improve over this performance penalty by storing, updating, and looking up the required information in a hash table. the keys are constructed from jittered and quantized information, such that only a single query very likely replaces costly neighborhood searches. A massively parallel implementation of the algorithm is demonstrated on a graphics processing unit (GPU).

关键词： Integral equations Real-time light transport simulation Variance reduction Hashing Monte Carlo integration Massively parallel algorithms

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A review of IoT architectures in smart healthcare applications 7

A review of IoT architectures in smart healthcare applicatio...

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7th international conference on Fog and Mobile Edge Computing (FMEC)

作者： Arbaoui, Meriem Brahmia, Mohamed-El-Amine Rahmoun, Abdellatif Cole Super Informat LabRi SBA Lab Sidi Bel Abbes Algeria CESI Engn Sch CESI LINEACT UR 7527 Strasbourg France

ISBN: (纸本)9798350334524

the Internet of things (IoT) is revolutionizing numerous industries, including healthcare services, known as the Internet of Medical things (IoMT). A large amount of generated data in IoMT applications need to be transmitted, analyzed, and stored. Consequently, the cloud-only architecture was proposed as being the best-fit organizational infrastructure. Indeed, cloud capabilities of processing, networking, and storage are overwhelming properties that make it outperform classical solutions for decades when it comes to healthcare applications. Nevertheless, this architecture could not keep up with the evergrowing amount of biomedical data. One of the main drawbacks of cloud architecture is the large latency, which prevents it from delivering real-time alerts to save the patient's life in critical situations. In this context, edge and fog computing become good alternatives to reduce health data management complexity and latency and therefore increase their reliability. this paper proposes a review of the most recent healthcare applications based on edge and fog computing, respectively. the selected research works of this survey are classified into four categories depending on their use case application. Furthermore, a comparison study helps extract relevant insights from several recent papers in the current literature to highlight their methodologies and purposes. the main concern is to emphasize what features and properties are to be considered most when designing a distributed healthcare system in an edge-fog architecture. Finally, we present some challenges to be addressed in healthcare applications along with the uprising of new technologies.

关键词： Healthcare Internet of things (IoT) Internet of Medical things (IoMT) architecture cloud computing edge computing fog computing

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A customized convolutional neural network structure design based on Field-Programmable Gate Array

A customized convolutional neural network structure design b...

引用

Computer Information Science and Application Technology (CISAT), international conference on

作者： Jiahong Zhang Dejun Yin Nanjing University of Science and Technology Nanjing China

ISBN: (数字)9798350375107

ISBN: (纸本)9798350375114

In this paper, different hardware deployment schemes are designed to accelerate the overall reasoning process of convolutional neural network according to the characteristics of large amount of calculation in convolution layer and large amount of parameters in linear layer. For convolutional neural networks with fewer layers, the LUT multiplication circuit is used instead of the DSP multiplication and the parameters are fixed in the circuit to reduce the dependence on DSP and ROM resources. this makes it possible to achieve higher parallelism reasoning on FPGAs with fewer resources. In this paper, a reduced-order convolutional neural network is trained based on the MNIST training set. After 8bit quantization, it is deployed to the FPGA and the inference speed reaches $\mathbf{7. 3 5 6}$ us, which is 339 times faster than that of the CPU.

关键词： Training Quantization (signal) Convolution parallel processing throughput Cognition Table lookup Convolutional neural networks Field programmable gate arrays Read only memory

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Developing Predictive Models and GUI for Area & Power Estimation of PISO Shift Register for FPGAs

Developing Predictive Models and GUI for Area & Power Estima...

引用

international conference on Signal processing and Communication (ICSC)

作者： Radhika Gupta Priti Kumari Rashi Jaiswal Tukur Gupta Department of Electronics & Communication Engineering Ajay Kumar Garg Engineering College Ghaziabad India

ISBN: (数字)9798331511890

ISBN: (纸本)9798331511906

Shift registers with parallel-In Serial-Out (PISO) functionality are essential components in digital electronics. they ease data transmission and minimize the amount of wiring needed by converting parallel data into a serial format, and hence used in digital communications, signal processing, and data storage. the significance of these shift registers and their guiding principles is anticipated to grow as digital technology develops, highlighting the need for a thorough analysis of their design constraints. Hence, area and power being two main design constraints for digital circuits need to be estimated. these estimates can be made using current commercial tools, however doing so requires more time because full design cycles must be followed. therefore, challenges for designers lie in accurate estimation of resource utilization and power dissipation at the early stages of designing while working under a tight deadline. this paper develops area and power estimation models for PISO shift register circuit using the curve fitting and regression technique in MATLAB. Vivado Design Suite (2014.4) is used to simulate and synthesize these circuits for various input/output (I/O) configurations targeted to Zynq-family Field-Programmable Gate Array (FPGA) device (xc7z020clg484-1). Furthermore, a user-friendly graphical user interface (GUI) is developed using Python Tkinter prompting designers to enter minimum input parameters and providing quick estimates of look-up tables (LUTs), flip-flops (FFs) and total on-chip power. these values predicted using GUI are compared with those obtained using Vivado tool. Comparison results infer that estimation errors lie in a comparable range. Hence, the proposed models and GUI expedite the design process by early and accurate estimation of area and power for FPGA-based PISO shift registers.

关键词： Machine learning algorithms Signal processing algorithms Predictive models Shift registers Prediction algorithms Table lookup Resource management Integrated circuit modeling Field programmable gate arrays Graphical user interfaces

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Exploiting Co-execution with OneAPI: Heterogeneity from a Modern Perspective 27th

Exploiting Co-execution with OneAPI: Heterogeneity from a Mo...

引用

27th international European conference on parallel and Distributed Computing (Euro-Par)

作者： Nozal, Raul Bosque, Jose Luis Univ Cantabria Dept Comp Sci & Elect Santander Spain

ISBN: (纸本)9783030856656;9783030856649

Programming efficiently heterogeneous systems is a major challenge, due to the complexity of their architectures. Intel oneAPI, a new and powerful standards-based unified programming model, built on top of SYCL, addresses these issues. In this paper, oneAPI is provided with co-execution strategies to run the same kernel between different devices, enabling the exploitation of static and dynamic policies. On top of that, static and dynamic load-balancing algorithms are integrated and analyzed. this work evaluates the performance and energy efficiency for a well-known set of regular and irregular HPC benchmarks, using an integrated GPU and CPU. Experimental results show that co-execution is worthwhile when using dynamic algorithms, improving efficiency even more when using unified shared memory.

关键词： Heterogeneous computing parallel computing Co-execution Load balancing SYCL oneAPI DPC plus Scheduling HPC

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Reconfigurable HW-SW Co-design Platform for Lung Cancer Detection and Classification 34

Reconfigurable HW-SW Co-design Platform for Lung Cancer Dete...

引用

34th international conference on VLSI Design / 20th international conference on Embedded Systems (VLSID)

作者： Sharma, Ayushparth Lata, Kusum LNM Inst Informat Technol Jaipur Rajasthan India

ISBN: (纸本)9781665440875

High-performance electronics has fueled the rich emergence of medical imaging applications that led to the exponential growth in treatment and diagnostic solutions of various medical problems. High-throughput and Energy-efficient systems are required to enable the development of complex medical imaging applications. this article presents an energy-efficient hardware-software (HW-SW) co-design of a scalable and reconfigurable image segmentation/classification streaming-based processing platform explored at various design abstraction levels. Optimized algorithms and architectural techniques achieve significant savings in energy consumption and operational time. the proposed platform has been implemented on Xilinx Spartan-6 FPGA board and co-simulated with Xilinx system generator, enabled real-time processing of CT scans for pulmonary nodule detection. Optimized pipelining and scheduling have minimized the memory requirements to few kB. parallel architecture has been employed achieving 10x higher energy-efficiency compared to serial counterpart and reduced execution period by 70x. Clinical validation shows that parallel architecture introduces 5-7% error in nodule characteristic determination in comparison to serial one.

关键词： lung cancer detection delay structures medical image processing energy-efficient platform reconfigurability

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A Method for parallel Calculation of Radar Detection Capability Based on 3D Subdivision Grid 7

A Method for Parallel Calculation of Radar Detection Capabil...

引用

7th international conference on Computer and Information processing Technology, ISCIPT 2022

作者： Li, Yang Yang, Anran Chen, Luo College of Electronic Science and Technology National University of Defense Technology Hunan Changsha China Key Laboratory of Natural Resources Monitoring and Supervision in Southern Hilly Region Ministry of Natural Resources Hunan Changsha China

In the field of electromagnetic computation, the expression ability of two-dimensional spatial calculation methods is limited, and the three-dimensional spatial calculation methods are complex. the existing radar detection capability calculation methods cannot calculate the power density distribution of radars in space position, comprehensively, quickly enough to depict the real-time capabilities of radars. In order to improve computing performance (To solve these problems), this paper proposes a multi-level fast calculation method of radar detection capability based on three-dimensional (3D) subdivision grid. the algorithm uses a unified encoding method to divide the space at different levels. After that, a parallel computing model is established to quickly calculate the radar power density corresponding to its spatial position and bearing. the experimental results show that the algorithm can provide an efficient calculation method for the power density distribution of various actual radars at different particle sizes. © 2022 Copyright for this paper by its authors.

关键词： Tracking radar

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High Performance Portable Solver for Tridiagonal Toeplitz Systems of Linear Equations

High Performance Portable Solver for Tridiagonal Toeplitz Sy...

引用

26th international conference on parallel and Distributed Computing (Euro-Par)

作者： Dmitruk, Beata Stpiczynski, Przemyslaw Marie Curie Sklodowska Univ Inst Comp Sci Ul Akad 9 PL-20033 Lublin Poland

ISBN: (纸本)9783030715939;9783030715922

We show that recently developed divide and conquer parallel algorithm for solving tridiagonal Toeplitz systems of linear equations can be easily and efficiently implemented for a variety of modern multicore and GPU architectures, as well as hybrid systems. Our new portable implementation that uses OpenACC can be executed on both CPU-based and GPU-accelerated systems. More sophisticated variants of the implementation are suitable for systems with multiple GPUs and it can use CPU and GPU cores. We consider the use of both columnwise and row wise storage formats for two dimensional double precision arrays and show how to efficiently convert between these two formats using cache memory. Numerical experiments performed on Intel CPUs and Nvidia GPUs show that our new implementation achieves relatively good performance.

关键词： Tridiagonal Toeplitz systems parallel algorithms Vectorization Portability OpenACC Hybrid systems

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FleCSI 2.0: the Flexible Computational Science Infrastructure Project 27th

FleCSI 2.0: The Flexible Computational Science Infrastructur...

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27th international European conference on parallel and Distributed Computing (Euro-Par)

作者： Bergen, Ben Demeshko, Irina Ferenbaugh, Charles Herring, Davis Lo, Li-Ta Loiseau, Julien Ray, Navamita Reisner, Andrew Los Alamos Natl Lab Appl Comp Sci Grp CCS 7 Los Alamos NM 87545 USA Los Alamos Natl Lab Lagrangian Codes Grp XCP 1 Los Alamos NM 87545 USA

ISBN: (纸本)9783031061561;9783031061554

the FleCSI 2.0 programming system supports multiphysics application development through a runtime abstraction layer, and by providing core topology types that can be customized for specific numerical methods. the abstraction layer provides a single-source programming interface for distributed and shared-memory data parallelism through task and kernel execution, and has been demonstrated to introduce virtually no runtime overhead. FleCSI's core topology types represent a rich set of basic data structures that can be specialized to create applicationfacing interfaces for a variety of different physics packages. Using the FleCSI control and data models, it is straightforward to compose multiple packages to create full multiphysics applications. When used with a task-based backend, FleCSI offers extended runtime analysis that can increase task concurrency, facilitate load balancing, and allow for portability across heterogeneous computing architectures.

关键词： Multiphysics Computational science Applied mathematics Task-based runtimes Heterogeneity Performance portability Accelerators

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An MPI-based Algorithm for Mapping Complex Networks onto Hierarchical architectures 27th

An MPI-based Algorithm for Mapping Complex Networks onto Hie...

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27th international European conference on parallel and Distributed Computing (Euro-Par)

作者： Predari, Maria Tzovas, Charilaos Schulz, Christian Meyerhenke, Henning Humboldt Univ Berlin Germany Heidelberg Univ Heidelberg Germany

ISBN: (纸本)9783030856656;9783030856649

processing massive application graphs on distributed memory systems requires to map the graphs onto the system's processing elements (PEs). this task becomes all the more important when PEs have non-uniform communication costs or the input is highly irregular. Typically, mapping is addressed using partitioning, in a two-step approach or an integrated one. parallel partitioning tools do exist;yet, corresponding mapping algorithms or their public implementations all have major sequential parts or other severe scaling limitations. In this paper, we propose a parallel algorithm that maps graphs onto the PEs of a hierarchical system. Our solution integrates partitioning and mapping;it models the system hierarchy in a concise way as an implicit labeled tree. the vertices of the application graph are labeled as well, and these vertex labels induce the mapping. the mapping optimization follows the basic idea of parallel label propagation, but we tailor the gain computations of label changes to quickly account for the induced communication costs. Our MPI-based code is the first public implementation of a parallel graph mapping algorithm;to this end, we extend the partitioning library PARHIP. To evaluate our algorithm's implementation, we perform comparative experiments with complex networks in the million- and billion-scale range. In general our mapping tool shows good scalability on up to a few thousand PEs. Compared to other MPI-based competitors, our algorithm achieves the best speed to quality trade-off and our quality results are even better than non-parallel mapping tools.

关键词： Load balancing Process mapping Hierarchical architectures parallel label propagation

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