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18th international conference on algorithms and architectures for parallel processing, ICA3PP 2018

18th International Conference on Algorithms and Architecture...

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18th international conference on algorithms and architectures for parallel processing, ICA3PP 2018

ISBN: (纸本)9783030050627

the proceedings contain 191 papers. the special focus in this conference is on algorithms and architectures for parallel processing. the topics include: Incentivizing multimedia data acquisition for machine learning system;Toward performance prediction for multi-BSP programs in ML;exploiting the table of energy and power leverages;a semantic web based intelligent IoT model;Accelerating CNNs using optimized scheduling strategy;data analysis of blended learning in python programming;APs deployment optimization for indoor fingerprint positioning with adaptive particle swarm algorithm;deployment optimization of indoor positioning signal sources with fireworks algorithm;a study of sleep stages threshold based on multiscale fuzzy entropy;qoS-driven service matching algorithm based on user requirements;Blind estimation algorithm over fast-fading multipath OFDM channels;facial shape and expression transfer via non-rigid image deformation;p-schedule: Erasure coding schedule strategy in big data storage system;Answer aggregation of crowdsourcing employing an improved EM-based approach;a parallel fast fourier transform algorithm for large-scale signal data using apache spark in cloud;task offloading in edge-clouds with budget constraint;motion trajectory sequence-based map matching assisted indoor autonomous mobile robot positioning;towards the independent spanning trees in the line graphs of interconnection networks;POEM: Pricing longer for edge computing in the device cloud;mobility analysis and response for software-defined internet of things;Research on overload classification method for bus images based on image processing and SVM;DStore: A distributed cloud storage system based on smart contracts and blockchain;towards an efficient and real-time scheduling platform for mobile charging vehicles;Streaming ETL in polystore era.

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A Hybrid Resampling Technique with Adaptive Intervals Used in the parallel/Distributed Particle Filters 23

A Hybrid Resampling Technique with Adaptive Intervals Used i...

引用

Proceedings of the 2023 7th international conference on Computer Science and Artificial Intelligence

作者： Xudong Zhang Feng Gu Wei Zhong Chunyu Ai University of South Carolina Upstate USA The College of Staten Island USA

ISBN: (纸本)9798400708688

parallel/Distributed particle filters estimate the states of dynamic systems by using Bayesian interference and stochastic sampling techniques with multiple processing units (PUs). the sampling procedure and the resampling procedure alternatively execute to estimate the states in particle filters. there are two basic types of resampling techniques used in parallel/distributed particle filters. they are centralized resampling and decentralized resampling. the high communication between PUs in centralized resampling lowers the speedup factor in parallel computing but improves the estimation accuracy. the decentralized resampling can avoid the communication and improve the performance. Some types of hybrid resampling techniques mainly execute the decentralized resampling and only invoke the centralized resampling with constant intervals to achieve ideal performance without losing the estimation accuracy. However, the constant intervals cannot guarantee that the centralized resamplings are invoked timely. In this study, we proposed a hybrid resampling technique with adaptive intervals between centralized resamplings to overcome that issue. the experimental results indicate that the proposed hybrid resampling technique is able to improve the performance and the estimation accuracy.

关键词： adaptive resampling particle filters resampling sequential Monte Carlo methods

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Structured Pruning for Multi-Task Deep Neural Networks

Structured Pruning for Multi-Task Deep Neural Networks

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IEEE conference on Multimedia Information processing and Retrieval (MIPR)

作者： Siddhant Garg Lijun Zhang Hui Guan Adobe Inc. College of Information & Computer Sciences University of Massachusetts Amherst Amherst Massachusetts

ISBN: (数字)9798350351422

ISBN: (纸本)9798350351439

Although multi-task deep neural network (DNN) models have computation and storage benefits over individual single-task DNN models, they can be further optimized via model compression. Numerous structured pruning methods have already been developed that can readily achieve speedups in single-task models, but the pruning of multi-task networks has not yet been extensively studied. In this work, we investigate the effectiveness of structured pruning on multi-task models. We use an existing single-task filter pruning criterion and also introduce an MTL- based filter pruning criterion for estimating the filter importance scores. We prune the model using an iterative pruning strategy with both pruning methods. We show that, with careful hyper-parameter tuning, architectures obtained from different pruning methods do not have significant differences in their performances across tasks when the number of parameters is similar. We also show that iterative structure pruning may not be the best way to achieve a well-performing pruned model because, at extreme pruning levels, there is a high drop in performance across all tasks. But when the same models are randomly initialized and re- trained, they show better results.

关键词： Computational modeling Artificial neural networks Information processing Computer architecture Multitasking Iterative methods Tuning Periodic structures

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Batch Workflow Scheduling Optimization in Cloud Resource Environment

Batch Workflow Scheduling Optimization in Cloud Resource Env...

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international conference on Information Technologies in Engineering Education (Inforino)

作者： Victor Toporkov Dmitry Yemelyanov Artem Bulkhak Department of Computing Technologies National Research University “MPEI” Moscow Russia

ISBN: (数字)9798350371369

ISBN: (纸本)9798350371376

the constantly evolving cloud ecosystems are promising environments for the execution of science-intensive applications within the framework of the new concept of Workflow-as-a-Service (WaaS). WaaS platforms, being the so-called multitenant environments, provide efficient mechanisms for managing continuous and heterogeneous job-flows in cloud computing. However, in this scenario, along with the complexity of scheduling composite workflows, an additional problem arises to efficiently manage the cloud resources, that is, to determine the start and shutdown times of virtual resources, considering the available economic policy. To handle this problem, we propose a modification to the critical jobs method which has been the basis of the Systems Design course in the Department of Computing Technologies for over 15 years. the resulting solution combines several heuristics to optimize the cloud resource management for WaaS platforms and largely determined the successful completion of RSF project. Some experiments with the real-world workflows prove the optimization efficiency of the proposed approach.

关键词： Cloud computing Limiting Processor scheduling Genomics parallel processing Scheduling Resource management

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Locality: the 3rd Wall and the Need for Innovation in parallel architectures 34th

Locality: The 3rd Wall and the Need for Innovation in Parall...

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34th international conference on Architecture of Computing Systems (ARCS)

作者： Kogge, Peter M. Page, Brian A. Univ Notre Dame Notre Dame IN 46556 USA

ISBN: (纸本)9783030816827;9783030816810

In the past we have seen two major "walls" (memory and power) whose vanquishing required significant advances in architecture. this paper discusses evidence of a third wall dealing with data locality, which is prevalent in data intensive applications where computation is dominated by memory access and movement - not flops, Such apps exhibit large sets of often persistent data, with little reuse during computation, no predictable regularity, significantly different scaling characteristics, and where streaming is becoming important. Further, as we move to highly parallel algorithms (as in running in the cloud), these issues will get even worse. Solving such problems will take a new set of innovations in architecture. In addition to data on the new wall, this paper will look at one possible technique: the concept of migrating threads, and give evidence of its potential value based on several benchmarks that have scaling difficulties on conventional architectures.

关键词： Architecture parallelism Multi-threading

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An Architecture for Deploying Convolutional Neural Network-Based Quality Systems for Use in Production Environments in Additive Manufacturing 5

An Architecture for Deploying Convolutional Neural Network-B...

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5th ASTM international conference on Additive Manufacturing, ICAM 2020

作者： Jones, Oliver Holloway, Adam Young, Joe Morrison, Alex Milne, Katy Rahman, M. Mostafizur Turner, Nathanael The Manufacturing Technology Centre Ltd. Pilot Way Ansty Park CoventryCV7 9JU United Kingdom

ISBN: (纸本)9780803177215

Recent advances in convolutional neural networks have shown promise for a wide range of engineering applications including production quality assessment. this has been enabled in part by the availability of open-source algorithms and techniques such as transfer learning. Despite these factors, deploying these algorithms in production environments remains a challenge. the research presents an architecture for the deployment of convolutional neural network algorithms for the quality assessment of additive manufacturing (AM) build processes. the first iteration of this architecture has been implemented in a preproduction powder bed fusion AM facility at the National Centre for Additive Manufacturing in the UK. By demonstrating the application of this architecture on data generated from in-process monitoring data, the study hopes to reduce barriers faced when taking machine learning models from a laboratory concept to a production facility. By reviewing the latency of predictions, the study highlights that the additional proposed architectures may be viable for processing live production data for detection and control of defects. Finally, the study proposes that AM build machine manufacturers could provide a service-oriented architecture to encourage the implementation of in-process correction strategies. Copyright © 2022 by ASTM international, 100 Barr Harbor Drive, PO Box C700, West Conshohocken, PA 19428-2959.

关键词： 3D printing

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Integrating Multicore SVM With Enhanced Residual Networks for AI Content Recognition

Integrating Multicore SVM With Enhanced Residual Networks fo...

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Pattern Recognition and Artificial Intelligence (PRAI), international conference on

作者： HaiQing Zhang Computer and Software Department Chengdu Jincheng College Chengdu Sichuan China

ISBN: (数字)9798350350890

ISBN: (纸本)9798350350906

this study delves into the intersection of data science and machine learning methodologies, specifically examining the recognition of Artificial Intelligence (AI)-generated papers and images. We curate a comprehensive dataset comprising 200 papers and 855 images, meticulously segregating them into AI-generated and non-AI categories, and transform this raw data into structured formats suitable for rigorous analysis. For text classification, we employ a Multicore Support Vector Machines (SVM) model, optimized through cross-validation and grid search techniques, to accurately distinguish AI-authored papers from human-penned ones. For image classification, we develop an enhanced model that builds upon the strengths of ResNet and DenseNet architectures, achieving high accuracy in discerning AI-generated images. Furthermore, we integrate these two classification systems within a weighted, top-level decision framework, offering a holistic approach to AI content recognition. the proposed methodology and findings offer a novel perspective on AI content detection, with potential applications in copyright protection, academic integrity assessment, and media content monitoring. this research contributes to advancing the state-of-the-art in AI content identification and underscores the importance of robust tools for managing the proliferation of AI-generated content.

关键词： Support vector machines Measurement Image recognition Accuracy Text recognition Multicore processing Writing Mathematical models Data models Artificial intelligence

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Design of Barker-7 Radar Pulse Compressor Using DSP Architecture Minimization Techniques

Design of Barker-7 Radar Pulse Compressor Using DSP Architec...

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international conference on Communication Systems and Network Technologies (CSNT)

作者： Anoopkumar K A Dayananda B N Achala G Pathipati Srihari Bethi Pardhasaradhi Linga Reddy Cenkeramaddi ECE Dept. National Institute of Technology Karnataka India Department of ICT University of Adger Grimsted Norway

ISBN: (数字)9798350305463

ISBN: (纸本)9798350305470

Pulse compression algorithms play an important role in achieving better range resolution (RR) in automobile radar and ultrasonic sensors. the RR is the sensor's capacity to distinguish between two targets positioned in the same angular direction but at different distances. the Digital Signal processing Architecture (DSPA) used in the pulse compressor is crucial for reaching high speeds or reducing hardware needs. this work presents two unique radar pulse compressor DSPAs for Barker-7 sequences, based on latency and area. One proposed design is the unfolding DSPA technology, which increases sample rate and speed. At the same time, another architecture, the folding DSPA approach, reduces hardware utilization and power consumption. the proposed DSPA design architectures are implemented and verified with the Artix-7 FPGA Kit. the unfolded Barker-7 pulse compressor increased the speed by 1.87 times as compared to the standard broadcasting Barker-7 realization, as demonstrated by the hardware implementation results. Folded Barker-7 architecture consumed 89% less power than existing Barker-7 broadcast architecture. the DSPAs proposed for the Barker-7 pulse compressor are ideal for ultrasonic, sonar, and radar applications that require high speed and low power.

关键词： Sonar applications Broadcasting Very large scale integration throughput Hardware Acoustics Radar applications

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A GPU Implementation of PRINCE Block Cipher

A GPU Implementation of PRINCE Block Cipher

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IEEE international conference on Computer and Communication Engineering Technology (CCET)

作者： Jingchun Yang Xin Jiang Songyan Xu Ran Tao Beijing Research Institute of Telemetry Beijing China Southeast University Suzhou China

ISBN: (数字)9798350355673

ISBN: (纸本)9798350355680

Owing to the drastic demand of cryptographic primitives for resource-constrained environments, lots of lightweight cipher designs sprout up in the last twenty years. PRINCE is a hardware-oriented block cipher which meets the low-latency encryption demand and has a compact design fashion. Many hardware implementations were proposed, however, there are few software implementations optimized for PRINCE. In this paper, we show that how to accelerate the software performance of the PRINCE block cipher using GPU programming. Our implementation involves the process of transferring the data between CPU and GPU, and the parallel executions of PRINCE kernel on GPU. Some optimizing techniques are adopted in our implementation, such as combining multiple looking-up-tables, function simplification, allocating suitable memories for different components and speeding up the memory access, using unified memory management to speed up the data transfer, and optimizing the size of the thread block. With a GTX 1070 GPU card on a common laptop, the throughput of the whole data processing reaches to about 64 Gbps, which speeds up about 4000 times compared to the original CPU implementation.

关键词： Ciphers Instruction sets Memory management Graphics processing units Software performance throughput Data transfer Real-time systems Encryption Kernel

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Review of Hardware Implementations of Convolution for Discrete Wavelet Transform

Review of Hardware Implementations of Convolution for Discre...

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North Karnataka Subsection Flagship international conference (NKCon), IEEE

作者： Ramprakash C Skanda Prasad Pratyusha R Raghu Jayaramu Department of Electronics and Communication Engineering The National Institute of Engineering Mysuru India

Field programmable gate arrays (FPGAs) have often been used as hardware accelerators for digital signal processing (DSP) algorithms such as convolution and filtering operations. this work is a review of hardware implementations of the convolution operation specific to the discrete wavelet transform (DWT). For such applications, read-only memory (ROM)-based architectures are known for their speed and performance. Two such architectures-distributed arithmetic (DA) and residue number system (RNS) are reviewed. Hardware utilization of both architectures using similar inputs and parameters on the Digilent Nexys-A7-100T field programmable gate array (FPGA) platform using Xilinx Vivado and other open-source tools are reported. Distributed arithmetic (DA) is found to be favourable for small input lengths, but residue number system (RNS) will surpass it for larger input lengths. A parallel distributed arithmetic (DA) implementation is also implemented, that offers significant computational speed-up at minimal power cost.

关键词： Convolution Signal processing algorithms Computer architecture Transforms Digital signal processing Logic gates Discrete wavelet transforms

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