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Review of Hardware Implementations of Convolution for Discrete Wavelet Transform

Review of Hardware Implementations of Convolution for Discre...

引用

North Karnataka Subsection Flagship international conference (NKCon), IEEE

作者： Ramprakash C Skanda Prasad Pratyusha R Raghu Jayaramu Department of Electronics and Communication Engineering The National Institute of Engineering Mysuru India

Field programmable gate arrays (FPGAs) have often been used as hardware accelerators for digital signal processing (DSP) algorithms such as convolution and filtering operations. this work is a review of hardware implementations of the convolution operation specific to the discrete wavelet transform (DWT). For such applications, read-only memory (ROM)-based architectures are known for their speed and performance. Two such architectures-distributed arithmetic (DA) and residue number system (RNS) are reviewed. Hardware utilization of both architectures using similar inputs and parameters on the Digilent Nexys-A7-100T field programmable gate array (FPGA) platform using Xilinx Vivado and other open-source tools are reported. Distributed arithmetic (DA) is found to be favourable for small input lengths, but residue number system (RNS) will surpass it for larger input lengths. A parallel distributed arithmetic (DA) implementation is also implemented, that offers significant computational speed-up at minimal power cost.

关键词： Convolution Signal processing algorithms Computer architecture Transforms Digital signal processing Logic gates Discrete wavelet transforms

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Performance Evaluation of Image Enhancement Techniques on Transfer Learning for Touchless Fingerprint Recognition

Performance Evaluation of Image Enhancement Techniques on Tr...

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international conference on Signal processing and Information Security (ICSPIS)

作者： S Sreehari P D Dilavar S M Anzar Alavikunhu Panthakkan Saad Ali Amin Department of Electronics and Communication TKM College of Engineering Kollam India APJ Abdul Kalam Kerala Technological University Thiruvanaanthapuram Center for Artificial Intelligence TKM College of Engineering Kollam India College of Engineering and IT University of Dubai Dubai U.A.E

ISBN: (数字)9798350368673

ISBN: (纸本)9798350368680

Fingerprint recognition remains one of the most reliable biometric technologies due to its high accuracy and uniqueness. Traditional systems rely on contact-based scanners, which are prone to issues such as image degradation from surface contamination and inconsistent user interaction. To address these limitations, contactless fingerprint recognition has emerged as a promising alternative, providing non-intrusive and hygienic authentication. this study evaluates the impact of image enhancement techniques on the performance of pre-trained deep learning models using transfer learning for touchless fingerprint recognition. the IIT-Bombay Touchless and Touch-Based Fingerprint Database, containing data from 200 subjects, was employed to test the performance of deep learning architectures such as VGG-16, VGG19, Inception-V3, and ResNet-50. Experimental results reveal that transfer learning methods with fingerprint image enhancement (indirect method) significantly outperform those without enhancement (direct method). Specifically, VGG-16 achieved an accuracy of 98% in training and 93% in testing when using the enhanced images, demonstrating superior performance compared to the direct method. this paper provides a detailed comparison of the effectiveness of image enhancement in improving the accuracy of transfer learning models for touchless fingerprint recognition, offering key insights for developing more efficient biometric systems.

关键词： Training Performance evaluation Accuracy Surface contamination Transfer learning Fingerprint recognition Signal processing Reliability Image enhancement Testing

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Accelerating blockwise parallel language models with draft refinement 24

Accelerating blockwise parallel language models with draft r...

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Proceedings of the 38th international conference on Neural Information processing Systems

作者： Taehyeon Kim Ananda theertha Suresh Kishore Papineni Michael Riley Sanjiv Kumar Adrian Benton KAIST AI Google Research

ISBN: (纸本)9798331314385

Autoregressive language models have achieved remarkable advancements, yet their potential is often limited by the slow inference speeds associated with sequential token generation. Blockwise parallel decoding (BPD) was proposed by Stern et al. [42] as a method to improve inference speed of language models by simultaneously predicting multiple future tokens, termed block drafts, which are subsequently verified by the autoregressive model. this paper advances the understanding and improvement of block drafts in two ways. First, we analyze token distributions generated across multiple prediction heads. Second, leveraging these insights, we propose algorithms to improve BPD inference speed by refining the block drafts using task-independent n-gram and neural language models as lightweight rescorers. Experiments demonstrate that by refining block drafts of open-sourced Vicuna and Medusa LLMs, the mean accepted token length are increased by 5-25% relative. this results in over a 3x speedup in wall clock time compared to standard autoregressive decoding in open-source 7B and 13B LLMs.

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A parallelized Clustering Method for High-dimensional Power Multilevel Data Resources in load changes Mode

A Parallelized Clustering Method for High-dimensional Power ...

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Energy, Electrical and Power Engineering (CEEPE), international conference on

作者： Guoliang Qian Jiahui Zhang Zilong Deng Qinbin Huang Leijian Hu Technology Department (of State Grid Zhejiang) State Grid Zhejiang Pinghu City Electric Power Supply Co. Ltd. Pinghu China Technology Department (of State Grid Zhejiang) Pinghu General Electric Installation Co. Ltd. Pinghu China

ISBN: (数字)9798350375794

ISBN: (纸本)9798350375800

Conventional parallelized clustering methods for high-dimensional electric power multilevel data resources are based on a single data feature, which cannot meet the demand of parallelized clustering. therefore, a parallelized clustering method for high-dimensional power multilevel data resources under load changes mode is designed. the sparse features of high-dimensional electric power multilevel data resources are extracted, and the high-dimensional electric power data are changed into low-dimensional observation data to reduce the data dimensions and solve the optimal sparse subspace, so as to satisfy the demand of parallel clustering of electric power resources. the parallelized clustering center of high-dimensional electric power multilevel data resources is established based on load changes, and the high-dimensional electric power multilevel data resources are optimized by parallel genetic algorithm, and whether the electric power data belongs to the value domain is detected, so as to realize the accurate clustering of data resources. Comparison experiments are used to verify that the method has better parallelized clustering effect and can be applied in real life.

关键词： Power engineering Clustering methods Distributed databases Feature extraction Data processing Explosives Power systems

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An Efficient LRnLA Algorithm and Data Structure for Manycore and Multicore Computers with Hierarchical Cache 17th

An Efficient LRnLA Algorithm and Data Structure for Manyco...

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17th international Scientific conference on parallel Computational Technologies, PCT 2023

作者： Levchenko, Vadim Perepelkina, Anastasia Keldysh Institute of Applied Mathematics Moscow Russia

ISBN: (纸本)9783031388637

According to the Roofline model, low arithmetic intensity is the main performance bottleneck for multidimensional simulation with stencil data access. this bottleneck can be eliminated using LRnLA (locally recursive nonlocally asynchronous) algorithms, which take advantage of all levels of cache. We introduce the new algorithm FArShFold, a development of previously published Torre-type LRnLA algorithms by using data arrays aligned with a space-time wavefront. the novelty is in the distribution of data between threads and the decomposition in the time axis for parallelism. In this paper, we present the implementation of the algorithm for the solution of fluid dynamics problems with the LBM method and its scaling on AMD zen2/3 processor architectures. the obtained performance for single precision D3Q19 LBM is more than 1.4 GLUps on the AMD Ryzen R9 5950X processor. © 2023, the Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Graphics processing unit

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Moving Average Filter Block Implementation Using USP-Awadhoot Divider

Moving Average Filter Block Implementation Using USP-Awadhoo...

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international Baltic Electronics conference, BEC

作者： Udayan S. Patankar Miguel E. Flores Ants Koel Sunil Patankar TJS Department of Electronics TalTech Tallinn University of Technology Tallinn Estonia School of Electronics Don Bosco University Soyapango El Salvador Kavi Kulguru Kalidas Sanskrit University Ramtek India

ISBN: (数字)9798350365115

ISBN: (纸本)9798350365122

In IoT systems, compact, battery-operated circuitry, and rapid data transmission are essential for reducing power consumption and extending battery life. Efficient data transmission requires robust local data processing capabilities supported by appropriate arithmetic and logical units (ALU). Modern processors or field-programmable gate arrays (FPGA) with a suitable ALU are well-suited for meeting these demands. To ensure data quality, effective signal processing before transmission is crucial. A moving average filter (MAF) is an excellent choice for this purpose, providing a balance of speed and precision while utilizing minimal hardware resources, thereby reducing the chip area needed for implementation. this article describes the design and implementation of the moving average low pass filter using the area-efficient novel USP-Awadhoot divider. the proposed USP-Awadhoot divider requires 266 LUTs and 146 FFs for 8-bit implementation using Xilinx FPGA. the proposed moving average filter based on a novel USP-Awadhoot divider is implemented on Nexys A7 XC7A100T-1CSG324C FPGA boards with Xilinx Vivado Design Suite. It is suitable for the cost-effective implementation of IoT and battery-operated applications.

关键词： Program processors Power demand Low-pass filters Signal processing Batteries Table lookup parallel architectures Mobile applications Data communication Field programmable gate arrays

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Accelerating Graph Applications Using Phased Transactional Memory 27th

Accelerating Graph Applications Using Phased Transactional M...

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27th international European conference on parallel and Distributed Computing (Euro-Par)

作者： Morales, Catalina Munoz Murari, Rafael de Carvalho, Joao P. L. Honorio, Bruno Chinelato Baldassin, Alexandro Araujo, Guido Univ Estadual Campinas Inst Comp Campinas Brazil Univ Estadual Paulista UNESP Rio Claro Brazil

ISBN: (纸本)9783030856656;9783030856649

Due to their fine-grained operations and low conflict rates, graph processing algorithms expose a large amount of parallelism that has been extensively exploited by various parallelization frameworks. Transactional Memory (TM) is a programming model that uses an optimistic concurrency control mechanism to improve the performance of irregular applications, making it a perfect candidate to extract parallelism from graph-based programs. Although fast Hardware TM (HTM) instructions are now available in the ISA extensions of some major processor architectures (e.g., Intel and ARM), balancing the usage of Software TM (STM) and HTM to compensate for capacity and conflict aborts is still a challenging task. this paper presents a Phased TM implementation for graph applications, called Graph-Oriented Transactional Memory (GoTM). It uses a three-state (HTM, STM, GLOCK) concurrency control automaton that leverages both HTM and STM implementations to speed-up graph applications. Experimental results using seven well-known graph programs and real-life workloads show that GoTM can outperform other Phased TM systems and lock-based concurrency mechanisms such as the one present in Galois, a state-of-the-art framework for graph computations.

关键词： Hardware transactional memory Software transactional memory Graph processing Large-scale graphs

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IoT Revolutionization using Federated Learning and Decentralized AI on Edge Devices

IoT Revolutionization using Federated Learning and Decentral...

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international conference on Contemporary Computing and Informatics (IC3I)

作者： Diwakar Chaudhary S K Verma Sumit Pundir S Ranganathan V. Umadevi K Srinivasan Department of Management Mangalmay Institute of Management & Technology Greater Noida Uttar Pradesh India School of Business Management Noida International University Greater Noida Uttar Pradesh India Department of Computer Science and Engineering Graphic Era Deemed to be University Dehradun Uttarakhand India Department of Computer Science Nehru Memorial College (Autonomous) Affiliated to Bharathidasan University Trichy Tamil Nadu India Department of Commerce General Saveetha College of Liberal Arts and Sciences SIMATS Chennai Tamil Nadu India

ISBN: (数字)9798350350067

ISBN: (纸本)9798350350074

this research proposes a novel strategy for addressing the limitations of centralized architectures in IoT data processing. Traditional systems experience significant bandwidth use, privacy difficulties, and scalability issues. To address these difficulties, the proposed approach combines Federated Learning (FL) with Decentralized AI on Edge Devices (DAI-ED). By decentralizing processing duties and utilizing FL methods, data is kept local to edge devices, lowering latency and improving privacy. Deployment entails choosing AI-capable edge devices and configuring them for seamless integration. Secure communication techniques provide privacy throughout FL operations. Model optimization approaches help to improve efficiency even further. Compared to centralized systems, the results show higher model accuracy, decreased communication overhead, and increased resource utilization. the proposed system has an overall accuracy of $\mathbf{9 5 \%}$, with edge device accuracy at $\mathbf{9 4. 5 \%}$ and central server accuracy at $\mathbf{9 6 \%}$. Communication overhead during the training and inference phases is greatly minimized, with the proposed system requiring 150 MB per device against $\mathbf{4 0 0} \mathrm{MB}$ in centralized systems. the proposed system has low memory consumption and computational complexity, but it is very scalable.

关键词： Training Privacy Data privacy Accuracy Protocols Federated learning Data processing Artificial intelligence Optimization Load modeling

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RenderMiner: Mining Micro-Architecture Characteristics of Rendering Programs on GPGPU

RenderMiner: Mining Micro-Architecture Characteristics of Re...

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Software Engineering and Computer Science (CSECS), international conference on

作者： Peng Wang Kaiyuan Qi Dept. Cloud Computing Research and Development Inspur Group Co. Ltd Jinan Inspur Data Technology Co. Ltd Jinan China

ISBN: (数字)9798331522216

ISBN: (纸本)9798331522223

In recent years, page-table the applications of virtual reality, augmented reality and mixed reality have become more and more popular, all of which are essentially image rendering. Graphics rendering requires a lot of calculations to determine the rendering parameters of each pixel. However, how to reveal the micro-architecture characteristics of GPGPU to help architects increase optimization opportunities and improve the performance of microprocessors becomes imperative. In this article, we propose RenderMiner, a framework which comprehensively characterizes the GPGPU rendering programs at the instruction and memory levels. Specifically, we design instruction mix based on the SASS instruction set, instruction frequency, register reuse distribution and memory call stack to efficiently depict the micro-architecture characteristics of rendering programs and compare with the non-rendering programs. We use RenderMiner to analyze the inherent behaviors of rendering programs combined with machining learning methods through 60 CPU rendering programs, 34 GPU rendering programs, 52 GPU non-rendering programs such as Rodinia and Parboil, and some real-world workloads, such as V-Ray5 Benchmark, Blender, Octane and Kobra Vulkan. After analysis of the rendering programs and comparison with non-rendering programs and the real-world workloads, the key findings of our conclusion are as following: (1) the instruction mix of CPU rendering programs is totally different from that of MiBench, especially at the aspect of arithmetic operation, memory read, memory write and control flow. (2) the instruction-level parallel interval of the CPU rendering program is mainly concentrated from 3 to 6. (3) there is comparable instruction frequency among GPU rendering, Octane, Kobra vulkan and non-rendering programs. (4) the average total instruction count of GPU rendering programs is 355 times more than that of non-rendering programs. (5) the portion of floating point of GPU rendering programs, B

关键词： Time-frequency analysis Graphics processing units Mixed reality parallel processing Benchmark testing Rendering (computer graphics) Real-time systems Registers Optimization Software engineering

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Efficient architectures for planar and DC modes of intra prediction in HEVC 7

Efficient architectures for planar and DC modes of intra pre...

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7th international conference on Signal processing and Integrated Networks, SPIN 2020

作者： Lakshmi Aparna, P. National Institute of Technology Department of Electronics and Communication Surathkal Karnataka India

ISBN: (纸本)9781728154756

High efficiency video coding (HEVC) handles the ever increasing global video content with better compression efficiency. Complex partition and increased number of angular modes in intra prediction is one of the factors responsible to achieve this but at the expense of complex computations. In this work, we propose two hardware architectures, parallel Pipelined Architecture (PPA), and parallel Datapath Architecture (PDA) for the planar and direct current (DC) modes of intra prediction in HEVC. PPA supports a combination of pipelining and parallel schemes, reuses the multipliers to reduce the hardware resources. PDA includes datapath0 for planar mode and datapath1 for DC mode. they function in parallel. they support all the block sizes and implemented on Artix-7 field programmable gate array (FPGA). the implemented results show that PDA uses 20% fewer resources for block size 4, while PPA uses 20%, 46%, and 62% fewer resources for block sizes 8, 16, and 32, respectively. Detailed synthesis results show that PPA and PDA achieve a throughput of 8 pixels/clock cycle and hence can support 4K videos at 30 frames per second. © 2020 IEEE.

关键词： Efficiency

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