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检索条件"任意字段=7th International Conference on Algorithms and Architectures for Parallel Processing"

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Delay Margin Analysis of a Large-Scale Optimal Velocity Model using the parallel processing Delay Margin Finder (parDMF) 7

Delay Margin Analysis of a Large-Scale Optimal Velocity Mode...

引用

7th international conference on Control, Decision and Information Technologies (CoDIT)

作者： Wang, Duo Ramirez, Adrian Sipahi, Rifat Northeastern Univ Dept Mech & Ind Engn Boston MA 02115 USA Catedras CONACYT Mexico City 03940 DF Mexico IPICYT Div Appl Math San Luis Potosi 78216 San Luis Potosi Mexico

ISBN: (纸本)9781728159539

A connected vehicle model with delays due to human reaction times and sensing and communication lines is considered. In particular, we investigate how time delays affect the equilibrium stability of this model in large scale. We focus mainly on the delay margin (DM) of this equilibrium, i.e., the largest delay that the system can accommodate without losing stability. We present how DM is influenced by the sparsity of sensor and communication lines and the number of vehicles. Different from previous work, no assumption is imposed on the structure of the network topology;the large-scale dynamics is treated in a computationally efficient manner by utilizing our recently developed parallel processing computational tool Delay Margin Finder (parDMF).

关键词： Network topology

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High throughput FPGA implementation of Min-Sum LDPC Decoder Architecture for Wireless Communication Standards

High throughput FPGA implementation of Min-Sum LDPC Decoder ...

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Digital Signal processing and its Applications (DSPA), international conference on

作者： Pavel Nikishkin Ruslan Goriushkin Nikita Vinogradov Evgeny Likhobabin Vladimir Vityazev Ryazan State Radio Engineering University RSREU Ryazan Russia

this paper presents a min-sum decoder design for Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. the design is supported various LDPC Parity-Check matrices including the WiMAX (IEEE 802.16e) and the WiFi (IEEE 802.11n) standards matrices. New techniques such as pipelining of the decoding architecture core are proposed. these core calculate variable-to-check (VTC) and new check-to-variable (CTV) messages and also update estimate of posterior probabilities (APPs). the parallel multicore decoding architecture implies a prior shift of values based on the LDPC matrix and simultaneous calculation of values for the core. Proposed decoder is implemented on the Zynq-7000 Mini-ITX Evaluation Board (XC7Z100-2FFG900).

关键词： Multicore processing Signal processing algorithms WiMAX Probability throughput Parity check codes Decoding

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Tight Bound of parallel Request Latency for Erasure-Coded Distributed Storage System 20th

Tight Bound of Parallel Request Latency for Erasure-Coded Di...

引用

20th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Zou, Xingshun Li, Wei Shandong Univ Jinan Peoples R China

ISBN: (纸本)9783030602451;9783030602444

With big data analysis and cloud storage improving at an astonishing rate in recent years, more and more parallel computing and data analysis techniques are invented and applied to accessing data from a distributed storage system, which has noticeable differences with accessing data from a separate dedicated storage system. the first and the last processes of a data analysis task in a shared filesystem may have a remarkable gap in latency. the latency of parallel file requests from these processes, however, lacks analytical model especially when erasure code is employed as storage strategy. the main contribution of this work is development of a tight bound of parallel file request latency to give a theoretical upper bound of lantency. Additionally, an exact batch file chunk request analytical model in distributed systems adopting erasure code is studied by the technique of two embedded Markov chains, performance measures such as queue length distribution, waiting time distribution, etc. are derived in closed form. Experimental evaluation verifies accuracy of the theoretical upper bound on latency.

关键词： parallel file requests Distributed storage system Erasure code Queueing theory Latency Embedded Markov chain

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Near-Data FPGA-Accelerated processing of Collective and Inference Operations in Disaggregated Memory Systems 7

Near-Data FPGA-Accelerated Processing of Collective and Infe...

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IEEE/ACM 7th international Workshop on Heterogeneous High- Performance Reconfigurable Computing (H2RC) Part of international conference for High Performance Computing, Networking, Storage and Analysis (SC)

作者： Heinz, Carsten Koch, Andreas Tech Univ Darmstadt Embedded Syst & Applicat Grp Darmstadt Germany

ISBN: (纸本)9781665446648

With growing data set sizes, many scientific and data center HPC workloads observe an increasing scaling imbalance, e.g., between compute and memory capacities. As a solution, disaggregated system architectures employ spatial distribution of the different resources. they aim for independent scaling of the different resource kinds (e.g., compute, non-volatile storage, memory), and use fast communication fabrics for their interconnection. However, for some bulk operations, such as reductions and collections, it is still beneficial to perform them close to the memories, avoiding the need to move large volumes of data over the fabric. this work realizes a disaggregated system capable of performing such near-data processing (NDP) operations by extending the distributed memory controllers with hardware-accelerated compute capabilities. the actual computations execute on FPGAs and can be abstractly described using C/C++ as compilable by high-level hardware synthesis (HLS) tools. We have aimed for high usability of our technology also by HPC experts unfamiliar with hardware design. An automated toolflow encapsulates the creation and deployment of the actual accelerators in the disaggregated system. the NDP operations execute distributed across all memory nodes, and are easily accessed using a simple MPI-based programming interface that requires only minimal effort to use in existing applications. Our solution is demonstrated using a prototype disaggregated system based on the low-latency EXTOLL fabric for communication. We evaluate both conventional reductions/collectives as well as complete machine-learning inference tasks.

关键词： Nonvolatile memory Memory management Systems architecture Prototypes Process control Programming Hardware

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parallel Belief Propagation Optimized by Coloring on GPUs 20th

Parallel Belief Propagation Optimized by Coloring on GPUs

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20th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Hou, Junteng Si, Chengxiang Wang, Shupeng Wu, Guangjun Zhang, Lei Chinese Acad Sci Inst Informat Engn Beijing Peoples R China Univ Chinese Acad Sci Sch Cyber Secur Beijing Peoples R China Coordinat Ctr China Natl Comp Network Emergency Response Tech Team Beijing Peoples R China

ISBN: (纸本)9783030602451;9783030602444

Belief propagation (BP) is a message passing algorithm that infers over probabilistic graphical models. Its main computational workload, messages update, is suitable for GPU's massively parallel architecture. However, the efficiency of fully parallel BP is low, and traditional algorithms implemented on GPUs occupy amount of computing and memory resources. In this paper, we propose several GPU-friendly BP algorithms optimized by coloring. Color Wave (CW) algorithm performs multi-step coloring on residuals of non-convergent vertices to quickly obtain multiple disjoint partitions and vertices with the largest residuals in each partition, and then updates batches of messages in a fixed order. these operations are all suitable for parallelization and require little additional memory. To save time in each iteration, the Color Extract (CE) algorithm only update messages on edges with the largest residuals among all adjacent edges. the Random Drop (RD) algorithm steadily increases the convergence degree by progressively reducing the messages update ratio of non-convergent edges. the experiments on different GPUs show that our algorithms perform well throughout the calculation process. Compared with state-of-the-art algorithms, CW algorithm converged most of the messages in previous iterations. the convergence degree of CE is higher than all other algorithms in most calculation processes. RD converges fast and always has a high degree of convergence.

关键词： Belief propagation GPUs parallel optimization Coloring operations Progressively reducing update ratio

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Ultra Low Power High Speed DFT Implementation For ASIC SoC

Ultra Low Power High Speed DFT Implementation For ASIC SoC

引用

international conference for Convergence of Technology (I2CT)

作者： K. Madhava Rao Pattem Sampath Kumar T. Vasudeva Reddy D Nilima K Saikumar Abbas Mahdi Khlaif Dept of ECE B V Raju Institute of Technology Narsapur Medak Telangana Department of ECE Malla Reddy College of Engineering Maisammaguda Dhulapally Secunderabad Department of Computer Science and Information Technology MLR Institute of Technology Hyderabad Telangana India Computer Science School of Engineering Malla Reddy University Maisammaguda Dulapally Hyderabad Telangana Scientific Research Center Al-Ayen University Thi-Qar Iraq

ISBN: (数字)9798350394474

ISBN: (纸本)9798350394481

An ultra-low power DFT architecture suitable for MIMO-OFDM applications & it was introduced in this study. Several radix such as 8/16/32 dependent optimization methods are performed to create variable lengths of 4k/8k points, a necessity in today's 4G and 5G communication technologies, which are plagued by a number of power and performance concerns with DFT processors. these technologies are widely used but have a higher energy footprint than others. Consequently, this work uses a novel approach called "SBOX" and the concept of parallelism to boost performance and reduce power consumption, all of which are essential for an advanced DFT architecture. parallelism and the proposed SBOX model allow for fewer multiplications and faster processing times. Cadence-allegro-17.2 is used for the design and verification of the full implementation; this software is also used for simulation, synthesis, layout, and power analysis. the area required for 8-point s-box DFT is 105.15 um2, it requires 7mW of power, and it can achieve a throughput of 59.33GBPS. In addition, the throughput of 57.33GBPS may be achieved by 16-point s-box DFT with a footprint of 123.35um2, using 9mW of power. Also, the throughput of 32-point s-box DFT is 56.45GBPS on a chip that uses 10.24 mW and occupies 132.35um2. With MIMO in 5G technology, this layout becomes more practical for usage in telecommunications. the performance is enhanced over existing architectures thanks to the optimized radix 8 s-box DFT.

关键词： 5G mobile communication Discrete Fourier transforms Layout Computer architecture parallel processing throughput Software

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A Binary Code Sequence Based Tracking Algorithm in Wireless Sensor Networks 19th

A Binary Code Sequence Based Tracking Algorithm in Wireless ...

引用

19th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Zhang, Yang Ren, Qianqian Pan, Yu Li, Jinbao Heilongjiang Univ Key Lab Database & Parallel Comp Heilongjiang Pro Harbin Peoples R China Heilongjiang Univ Key Lab Elect Engn Coll Heilongjiang Prov Harbin Peoples R China Heilongjiang Univ Sch Comp Sci & Technol Harbin Peoples R China

ISBN: (纸本)9783030389611;9783030389604

this paper proposes a binary code sequence based tracking algorithm in wireless sensor network. the proposed algorithm can release the influence of sensed data on localization results via building the map between target's occurrence region and a binary code sequence. To solve the ambiguity problem existing in occurrence region determination, the paper further gives a Voronoi diagram based location refinement algorithm. the simulation results show the tracking results under difference trajectories.

关键词： Target localization RSSI Voronoi

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Efficient parallel algorithms for betweenness- and closeness-centrality in dynamic graphs 34

Efficient parallel algorithms for betweenness- and closeness...

引用

34th ACM international conference on Supercomputing, ICS 2020

作者： Shukla, Kshitij Regunta, Sai Charan Tondomker, Sai Harsh Kothapalli, Kishore International Institute of Information Technology Hyderabad India

ISBN: (纸本)9781450379830

Finding the centrality measures of nodes in a graph is a problem of fundamental importance due to various applications from social networks, biological networks, and transportation networks. Given the large size of such graphs, it is natural to use parallelism as a recourse. there have been several studies that show how to compute the various centrality measures of nodes in a graph on parallel architectures, including multi-core systems and GPUs. However, as these graphs evolve and change, it is pertinent to study how to update the centrality measures on changes to the underlying graph. In this paper, we show novel parallel algorithms for updating the betweenness- and closeness-centrality values of nodes in a dynamic graph. Our algorithms process a batch of updates in parallel by extending the approach of handling a single update for betweenness-and closeness-centrality by Jamour et al. [16] and Sariyüce et al. [27], respectively. Besides, our algorithms incorporate mechanisms to exploit the structural properties of graphs for enhanced performance. We implement our algorithms on two parallel architectures: an Intel 24-core CPU and an Nvidia Tesla V100 GPU. To the best of our knowledge, we are the first to show GPU algorithms for the above two problems. We conduct detailed experiments to study the impact of various parameters associated with our algorithms and their implementation. Our results on a collection of real-world graphs indicate that our algorithms achieve a significant speedup over corresponding state-of-the-art algorithms. © 2020 ACM.

关键词： Graphics processing unit

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CC-MOEA: A parallel Multi-objective Evolutionary Algorithm for Recommendation Systems 20th

CC-MOEA: A Parallel Multi-objective Evolutionary Algorithm f...

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20th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Wei, Guoshuai Wu, Quanwang Chongqing Univ Coll Comp Sci Chongqing Peoples R China

ISBN: (纸本)9783030602390;9783030602383

Recommender systems have nowadays been widely used in a variety of applications such as Amazon and Ebay. Traditional recommendation techniques mainly focus on recommendation accuracy only. In reality, other metrics such as diversity and novelty also play a key role for modern recommendation systems. Although some works based on multi-objective evolutionary algorithm have been proposed for multi-objective recommendation, they are usually very time-consuming because of the large data size of the RSs and the long-term evolution iterations and hence it greatly limits their application in practice. To address these shortcomings, this paper first designs a multi-objective recommendation system, taking into account diversity and novelty as well as accuracy. then, a novel parallel multi-objective evolutionary algorithm called CC-MOEA is proposed to optimize these conflicting metrics. CC-MOEA is devised grounded on NSGA-II and a cooperative coevolutionary island model, and a parallel global non-dominated selection method is introduced to reduce the runtime of finding the global optimal individuals. Furthermore, a new initialization method and a crossover operator are specifically designed. the experimental results reveal that CC-MOEA outperforms some state-of-the-art algorithms in terms of hypervolume and runtime.

关键词： Accuracy Cooperative coevolutionary Multi-objective evolutionary algorithm parallel Recommendation system

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New adiabatic error tolerant adder i architectures 7

New adiabatic error tolerant adder i architectures

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7th international conference on Signal processing and Integrated Networks, SPIN 2020

作者： Kumar, Aditya S. Wadhwa, Abhishek Pandey, Neeta Delhi Technological University Department of Electronics and Communication Delhi India

ISBN: (纸本)9781728154756

this paper proposes two architectures of 16-bit Adiabatic Error Tolerant Adder I (ETA I). the first architecture is based on adaptation of ETA I in Adiabatic domain and is termed as AETA-I. the approximate part in AETA-I uses large number of buffers and its delay dominates the computation time, thus not fully utilizing the benefits of Approximate Computing. the second architecture addresses this issue by modifying AETA-I (META-I), processing propagate and generate bits rather than actual input values. this modification reduces the number of buffers significantly (3.42 times) and culminates into reduction in pipeline depth, power and area. the proposed adders are implemented using Positive Feedback Adiabatic Logic (PEAL) and are validated using 45nm PTM HP technology parameters in Tanner T-Spice™. For a wider comparison, PEAL based 16-bit Kogge Stone Adder (KSA) is also implemented. the proposed MAETA-I architecture has a maximum power savings of 44.94% and 30.33% at 50MHz when compared with Adiabatic KSA and AETA-I respectively. © 2020 IEEE.

关键词： Adders

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