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检索条件"任意字段=7th International Conference on Algorithms and Architectures for Parallel Processing"

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APR-16: the Physical Design of a Reconfigurable Array Processor Chip

APR-16: The Physical Design of a Reconfigurable Array Proces...

引用

international conference on Integrated Circuits and Microsystems (ICICM)

作者： Yangfan Xiao Rui Shan Zekun Ye Lin Jiang Wang Liao Baoxiang Zhang School of Electronic Engineering Xi’an University of Posts and Telecommunications Xi’an China School of Computer Science and Technology Xi’an University of science and technology Xi’an China Xi’an University of Posts and Telecommunications Xi’an China

ISBN: (纸本)9781665460583

In the physical chip design under the ultra-deep submicron (UDSM) process, interconnect delay, internal resistance drop (IR drop), and signal integrity (SI) has become the key factors affecting timing convergence and design cycle. this paper introduces a reconfigurable array processor architecture chip to solve the above problems. It discusses the requirements of the chip, the logic synthesis, and the physical design under the SMIC 55nm process in detail. First, four different timing optimization methods are employed to optimize the critical path that affects the timing, thus accelerating the execution time of the subsequent placement and routing. Secondly, the edge placement method based on data flow is adopted to reduce the interconnect length and delay of interconnection. Finally, the power network synthesis, placement, clock tree synthesis, and routing are completed. the results demonstrate that the working frequency can reach 320MHz. Meanwhile, the resource consumption is 80506 logic gates, and the chip area is 12mm 2 .

关键词： Windings Integrated circuit interconnections parallel processing Logic gates Routing Delays Logic arrays

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Optimizing B⁺-Tree Searches on Coupled CPU-GPU architectures 20th

Optimizing B<SUP>+</SUP>-Tree Searches on Coupled CPU-GPU Ar...

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20th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Huang, Han Luan, Hua Beijing Normal Univ Beijing Peoples R China

ISBN: (纸本)9783030602451;9783030602444

the B+-tree is an important index in the fields of data warehousing and database management systems. With the development of new hardware technologies, the B+-tree needs to be revisited to fully take advantage of hardware resources. In this paper, we focus on optimization techniques to increase the searching performance of B+-trees on the coupled CPU-GPU architecture. First, we propose a hierarchical searching approach on the single coupled GPU to efficiently deal with leaf nodes of B+-trees. It adopts a flexible strategy to determine the number of work items in a work group to search one key in order to reduce irregular memory accesses and divergent branches in the work group. Second, we present a co-processing pipeline method on the coupled architecture. the CPU and the integrated GPU process the sorting and searching tasks simultaneously to hide sorting and partial searching latencies. A distribution model is designed to support the workload balance strategy based on real-time performance. Our performance study shows that the hierarchical searching scheme provides an improvement up to 36% on the GPU compared to the baseline algorithm with fixed number of work items and the co-processing pipeline method further increases the throughput by a factor of 1.8. To the best of our knowledge, this paper is the first study to consider both the CPU and the coupled GPU to optimize B+-trees searches.

关键词： B+-trees the coupled architecture Integrated GPU Co-processing

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Studying the Performance of Vector-Based Quicksort Algorithm 13th

Studying the Performance of Vector-Based Quicksort Algorithm

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13th international conference on parallel processing and Applied Mathematics, PPAM 2019

作者： Marowka, Ami Parallel Research Lab Jerusalem Israel

ISBN: (纸本)9783030432218

the performance of parallel algorithms is often inconsistent with their preliminary theoretical analyses. Indeed, the difference is increasing between the ability to theoretically predict the performance of a parallel algorithm and the results measured in practice. this is mainly due to the accelerated development of advanced parallel architectures, whereas there is still no agreed model for parallel computation, which has implications for the design of parallel algorithms. In this study, we examined the practical performance of Cormen’s Quicksort parallel algorithm. We determined the performance of the algorithm with different parallel programming approaches and examine the capacity of theoretical performance analyses of the algorithm for predicting the actual performance. © 2020, Springer Nature Switzerland AG.

关键词： Python

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MULTI-GPU TRAINING and parallel CPU COMPUTING for the MACHINE LEARNING EXPERIMENTS USING ARIADNE LIBRARY 9

MULTI-GPU TRAINING and PARALLEL CPU COMPUTING for the MACHIN...

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9th international conference "Distributed Computing and Grid Technologies in Science and Education", GRID 2021

作者： Goncharov, Pavel Nikolskaia, Anastasiia Ososkov, Gennady Rezvaya, Ekaterina Rusov, Daniil Shchavelev, Egor Joint Institute for Nuclear Research 6 Joliot-Curie Street Dubna Moscow region 141980 Russia Saint Petersburg State University 7-9 Universitetskaya emb. Saint Petersburg199034 Russia

Modern machine learning (ML) tasks and neural network (NN) architectures require huge amounts of GPU computational facilities and demand high CPU parallelization for data preprocessing. At the same time, the Ariadne library, which aims to solve complex high-energy physics tracking tasks with the help of deep neural networks, lacks multi-GPU training and efficient parallel data preprocessing on the CPU. In our work, we present our approach for the Multi-GPU training in the Ariadne library. We will present efficient data-caching, parallel CPU data preprocessing, generic ML experiment setup for prototyping, training, and inference deep neural network models. Results in terms of speed-up and performance for the existing neural network approaches are presented with the help of GOVORUN computing resources. Copyright © 2021 for this paper by its authors. Use permitted under Creative Commons License Attribution 4.0 international (CC BY 4.0).

关键词： Graphics processing unit

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RISC-V processor-based automatic access floating-point computing accelerated dataflow co-processor

RISC-V processor-based automatic access floating-point compu...

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Science and Technology Innovation (IAECST), international Academic Exchange conference on

作者： Chao-Xing You Qi-Tong Wang Han Zhong Cheng Liu School of Microelectronics Shanghai University China

the Von Neumann and Harvard architectures are very efficient as the common structures of modern computers. However, they reach certain bottlenecks in parallelism, access speed, and power. In this paper, we propose a new architecture to further improve the parallelism and access speed of RISC-V computing system by adding data flow co-processors. the data flow coprocessor in the architecture is further optimized according to the computational characteristics of modern convolutional neural networks. the computation speed of floating- point numbers is increased to further improve the usefulness of the architecture. the data flow coprocessor adds an automatic access mechanism to further relieve the computational pressure on the main processor. Finally, experiments are conducted on the structure with the NEXYS A7 100t FPGA development board to verify the feasibility of the system.

关键词： Computers Technological innovation Computer architecture parallel processing Convolutional neural networks Field programmable gate arrays Coprocessors

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Memory Network Architecture for Packet processing in Functions Virtualization

Memory Network Architecture for Packet Processing in Functio...

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IEEE conference on Network Softwarization (NetSoft)

作者： Tomohiro Korikawa Eiji Oki Graduate School of Informatics Kyoto University Kyoto Japan

Packet processing tasks in network functions issue memory requests to understand the packet information, update the packet content, and search the databases, which requires high-performance memory systems. While network functions virtualization (NFV) is expected to reduce the cost of network infrastructure by replacing dedicated network equipment with commercial off-the-shelf (COTS) hardware and virtual network functions (VNFs), VNF performance suffers from the poor memory systems that lack function-dedicated memories and memory parallelism in COTS servers. While several works presented parallel memories for packet processing based on 3 dimensional (3D)-stacked dynamic random access memories (DRAMs), data transfer latency between the processors and memories are not considered. Although there are processing-in-memory (PIM) architectures that offload a part of processing in memories to reduce data transfers, the majority of processing is still in the processors, which requires data transfers for multiple packet processing tasks. this paper proposes a memory network architecture using 3D-stacked DRAMs to increase throughput and reduce accumulated latency when there are multiple packet processing tasks. Packets that enter the memory network receive packet processing at each 3D-stacked DRAM without data transfers between the processors and memories. the evaluation results show that the proposed architecture increases throughput and reduces accumulated latency for memory accesses and data transfers when there are multiple packet processing tasks, compared to the conventional architecture with 3D-stacked DRAM-based parallel memory, where every memory access requires data transfers.

关键词： Program processors Memory management Random access memory Telecommunication traffic Data transfer throughput Network function virtualization

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Structural Balance Computation in Signed Networks by Using Multifactorial Discrete Particle Swarm Optimization

Structural Balance Computation in Signed Networks by Using M...

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IEEE international conference on Cloud Computing and Intelligence Systems (CCIS)

作者： Changlong He Zengyang Shao Lijia Ma Jianqiang Li Tingyi Hu College of Computer Science and Software Engineering Shenzhen University Shenzhen China

ISBN: (纸本)9781665441506

the signed network has received widespread attention because it can well reflect the cooperation and conflict relationship. Structural balance is an important global feature in signed networks, which can well reflect the structural characteristics of the network. Existing structural balance calculation algorithms define the global and local balance computation problems as an optimization problem, and then optimize their respective objective functions through optimization algorithms, but these algorithms ignore the correlation between the two problems. In this paper, we combine the multifactorial evolutionary algorithm and the discrete particle swarm optimization algorithm, and further propose the multifactorial discrete particle swarm optimization algorithm (MFDPSO). this algorithm designs the knowledge transfer function and optimization algorithm based on the correlation of the strong and weak structure balance and optimizes the two problems at the same time. the experimental results on 8 real networks demonstrate the effectiveness of the MFDPSO.

关键词： Correlation parallel processing Search problems Linear programming Stability analysis Particle swarm optimization Task analysis

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A Distributed Framework for Online Stream Data Clustering 20th

A Distributed Framework for Online Stream Data Clustering

引用

20th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Ding, Jiafeng Fang, Junhua Chao, Pingfu Xu, Jiajie Zhao, PengPeng Zhao, Lei Soochow Univ Dept Comp Sci & Technol Suzhou Peoples R China Univ Queensland Brisbane Qld Australia

ISBN: (纸本)9783030602451;9783030602444

the recent prevalence of positioning sensors and mobile devices generates a massive amount of spatial-temporal data from moving objects in real-time. As one of the fundamental processes in data analysis, the clustering on spatial-temporal data creates various applications, like event detection and travel pattern extraction. However, most of the existing works only focus on the offline scenario, which is not applicable to online time-sensitive applications due to their low efficiency and ignorance of temporal features. In this paper, we propose a distributed streaming framework for spatial-temporal data clustering, which accepts various clustering algorithms while ensuring low resource consumption and result correctness. the framework includes a dynamic partitioning strategy for continuous load-balancing and a cluster-merging algorithm based on convex hulls [10], which guarantees the result correctness. Extensive experiments on real dataset prove the effectiveness of our proposed framework and its advantage over existing solutions.

关键词： Real-time cluster analysis Distributed stream processing Spatial-temporal data mining Top-k query parallel computing

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Reconfigurable HW-SW Co-design Platform for Lung Cancer Detection and Classification

Reconfigurable HW-SW Co-design Platform for Lung Cancer Dete...

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international conference on VLSI Design

作者： Ayushparth Sharma Kusum Lata The LNM Institute of Information Technology Jaipur India

High-performance electronics has fueled the rich emergence of medical imaging applications that led to the exponential growth in treatment and diagnostic solutions of various medical problems. High-throughput and Energy-efficient systems are required to enable the development of complex medical imaging applications. this article presents an energy-efficient hardware-software (HW-SW) co-design of a scalable and reconfigurable image segmentation/classification streaming-based processing platform explored at various design abstraction levels. Optimized algorithms and architectural techniques achieve significant savings in energy consumption and operational time. the proposed platform has been implemented on Xilinx Spartan-6 FPGA board and co-simulated with Xilinx system generator, enabled real-time processing of CT scans for pulmonary nodule detection. Optimized pipelining and scheduling have minimized the memory requirements to few kB. parallel architecture has been employed achieving 10× higher energy-efficiency compared to serial counterpart and reduced execution period by 70 ×. Clinical validation shows that parallel architecture introduces 5-7 % error in nodule characteristic determination in comparison to serial one.

关键词： Memory management Lung cancer Very large scale integration Streaming media Energy efficiency Real-time systems parallel architectures

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SCALPsim, a tool for modeling asynchronous Self-Organizing 3-D NoC architectures 27

SCALPsim, a tool for modeling asynchronous Self-Organizing 3...

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27th IEEE international conference on Electronics, Circuits and Systems (IEEE ICECS)

作者： Barrientos, Diego Sousa, Claudio Upegui, Andres Girau, Bernard Univ Appl Sci Western Switzerland Geneva Switzerland Univ Lorraine LORIA UMR 7503 CNRS Vandoeuvre Les Nancy France

ISBN: (纸本)9781728160443

Manycore architectures are mainly composed of a very large amount of computing nodes interconnected with a multiplicity of links usually forming a NoC-like mesh architecture. High-speed links permit to obtain a higher throughput but are much more expensive than normal links, making the interconnection of the system a cost/performance trade-off. Simulating such architectures is very important in order to characterise the optimal network topology for a given problem. In this work we introduce SCALPsim: a simulation framework permitting to evaluate routing algorithms and network properties in 1-D, 2-D and 3-D regular mesh topologies simultaneously using links of different characteristics in terms of latency and throughput. these features are particularly interesting in large scale systems with processing elements grouped into clusters, where communication properties differ largely inside and between clusters. this paper presents the framework and an application based on Cellular Self-Organizing Maps - CSOM.

关键词： Cellular Self-Organising Maps parallel computation multi-FPGA

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