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Distributed and parallel Ensemble Classification for Big Data Based on Kullback-Leibler Random Sample Partition 20th

Distributed and Parallel Ensemble Classification for Big Dat...

引用

20th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Wei, Chenghao Zhang, Jiyong Valiullin, Timur Cao, Weipeng Wang, Qiang Long, Hao Shenzhen Univ Big Data Inst Coll Comp Sci & Software Engn Shenzhen 518000 Peoples R China Hangzhou Dianzi Univ Sch Automat Hangzhou 311305 Peoples R China Southern Univ Sci & Technol SUSTech Acad Adv Interdisciplinary Studies Shenzhen 518055 Peoples R China

ISBN: (纸本)9783030602451;9783030602444

In this article, we use a Kullback-Leibler random sample partition data model to generate a set of disjoint data blocks, where each block is a good representation of the entire data set. Every random sample partition (RSP) block has a sample distribution function similar to the entire data set. To obtain the statistical measure between them, Kernel Density Estimation (KDE) with a dual-tree recursion data structure is firstly applied to fast estimate the probability density of each block. then, based on the Kullback-Leibler (KL) divergence measure, we can obtain the statistical similarity between a randomly selected RSP data block and other RSP data blocks. We rank the RSP data blocks according to their divergence values in descending order and choose the first ten for an ensemble classification learning. the classification models are established in parallel for the selected RSP data blocks and the final ensemble classification model is obtained by the weighted voting ensemble strategy. the experiments were conducted by building XGboost model based on those ten blocks in parallel, and we incrementally ensemble them according to their KL values. the testing classification results show that our method can increase the generalization capability of the ensemble classification model. It could reduce the model building time in parallel computation environment by using less than 15% of the entire data, which could also solve the memory constraints of big data analysis.

关键词： Big data analysis Approximate computing Random sample partition Ensemble classification parallel distributed computing

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Performance Evaluation of Dual Drive Dual parallel Mach Zehnder Modulator Based Radio Over Fiber link for Wireless Networks

Performance Evaluation of Dual Drive Dual Parallel Mach Zehn...

引用

international conference on Signal processing and Communication (ICSC)

作者： Neetu Tyagi Parvin Kumar KIET Group of Institutions Delhi-NCR Ghaziabad (U.P.)-201206 India

ISBN: (纸本)9781665427401

In this research paper a method to realize a single side band technique in RoF link is demonstrated. Radio over Fiber (RoF) emerges as a part of optical communication system and it has wide variety of application. In spite of having wide variety of application performance parameter of RoF link is limited by non-linear behavior which degrades modulation performance and enhances inter modulation distortion (IMD). In this research paper third orders inter modulation distortion (IMD3) has taken into consideration and comparison is made in terms of IMD3 component suppression with respect to modulator: Single drive MZM and Dual drive dual parallel Mach zehnder modulator (DPMZM) in RoF link. For simulation of proposed model Optisystem software is used. From simulation outcomes, it is found that IMD3 suppressed more in DPMZM in comparison to the single drive MZM in RoF link.

关键词： Performance evaluation Wireless networks Nonlinear distortion Modulation Optical distortion Drives Optical fiber networks

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Cross-shard Transaction processing in Sharding Blockchains 20th

Cross-shard Transaction Processing in Sharding Blockchains

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20th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Liu, Yizhong Liu, Jianwei Yin, Jiayuan Li, Geng Yu, Hui Wu, Qianhong Beihang Univ Sch Elect & Informat Engn Beijing Peoples R China Beihang Univ Sch Cyber Sci & Technol Beijing Peoples R China Univ Copenhagen Dept Comp Sci Copenhagen Denmark

ISBN: (纸本)9783030602482;9783030602475

Sharding blockchains could improve the transaction throughput and achieve scalibility, making the application fields of the blockchain technology more extensive. Cross-shard transactions account for a large fraction of transactions in a sharding blockchain, so the processing method of cross-shard transactions is of vital importance to the system efficiency. In this paper, we focus on the study of cross-shard transaction processing methods. Firstly, a summary of cross-shard transaction processing methods for sharding blockchains is given. Secondly, we propose RSTBP, which is built on the basis of a two phase commit protocol. In RSTBP, an input shard runs an intra-shard consensus algorithm, i.e., a Byzantine fault tolerance (BFT) algorithm, to process multiple inputs of different transactions simultaneously. For each input, a corresponding proof of availability is generated and sent to the relevant shards. Compared with previous schemes, the number of BFT calls is reduced by hundreds of times when processing the same number of transactions. thirdly, RSTSBP is designed by making some modifications to RSTBP. the proofs of availability are constructed according to different shards. the Merkel tree structure is different from that of RSTBP to cut down message complexity of the proofs. Both of the two schemes are proved to satisfy the consistency, liveness and responsiveness properties, and improve the cross-shard transaction processing efficiency.

关键词： Sharding blockchains Byzantine fault tolerance Cross-shard transactions Scalability Responsiveness

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Modeling and Analysis of Partitions on Functional architectures Using EAST-ADL 1

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7th international conference on Model-Driven Engineering and Software Development (MODELSWARD)

作者： Etzel, Christoph Bauer, Bernhard Univ Augsburg Inst Comp Sci Augsburg Germany

ISBN: (数字)9783030378738

ISBN: (纸本)9783030378738;9783030378721

the complexity in automotive systems engineering is increasing over the last decade. Autonomous driving and new comfort functions are some reasons for this growing complexity. With the introduction of multi-core processors in automotive system architectures, the shift from sequential to parallel thinking is more and more important in the different development phases. Based on the EAST-ADL, we present an approach to support the design process for distributed systems by using partitioning as an additional viewpoint on the architecture level. therefore, we developed an extension to the EAST-ADL for partitioning and show automatic partitioning analysis on different architecture abstractions. these derived partitions can support system designers during the design process of functional architectures, by having a first insight how independent the functional components are structured from a data dependency viewpoint. this gives hints for the allocation of functions to hardware in later stages of the development process.

关键词： System architecture Model-driven systems engineering Automotive systems engineering

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Accelerating Nested Data parallelism: Preserving Regularity 26th

Accelerating Nested Data Parallelism: Preserving Regularity

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26th international conference on parallel and Distributed Computing (Euro-Par)

作者： van den Haak, Lars B. McDonell, Trevor L. Keller, Gabriele K. de Wolff, Ivo Gabe Eindhoven Univ Technol Eindhoven Netherlands Univ Utrecht Utrecht Netherlands

ISBN: (纸本)9783030576752;9783030576745

Irregular nested data-parallelism is a powerful programming model which enables the expression of a large class of parallel algorithms. However, it is notoriously difficult to compile such programs to efficient code for modern parallel architectures. Regular data-parallelism, on the other hand, is much easier to compile to efficient code, but too restricted to express some problems conveniently or in a manner to exploit the full parallelism. We extend the regular data-parallel programming model to allow for the parallel execution of array-level conditionals and iterations over irregular nested structures, and present two novel static analyses to optimise the code generated for these programs which reduces the costs of this more powerful irregular model. We present benchmarks to support our claim that these extensions are effective as well as feasible, as they enable to exploit the full parallelism of an important class of algorithms, and together with our optimisations lead to an improvement in absolute performance over an implementation limited to exploiting only regular parallelism.

关键词： Arrays GPGPU Nested data parallelism parallel functional programming

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A FPGA-based Design and Implementation of Satellite Ground Fusion Downlink

A FPGA-based Design and Implementation of Satellite Ground F...

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international conference on Computer and Communications (ICCC)

作者： Yang Shi Cheng Wang Jianfei Tong Xiaoyan Zhao Weidong Wang School of Electronic Engineering Beijing University of Posts and Telecommunications Beijing China

ISBN: (纸本)9781665409513

Satellite ground fusion network has the advantages of broad coverage of satellite network and high-speed transmission link of ground network. It can realize communication access in peak hours in complex scenarios and meet the growing communication needs of high-speed and large capacity. Whether the downlink can accurately recover and analyze the signal is the key to the whole link. this paper designs a downlink receiver processing flow based on the combination of the standard protocol and FPGA (Field Programmable Gate Array). the processing of received data mainly includes symbol-level processing and bit-level processing. the data processing of the whole receiving end is completed through the transmission processing of data between each module. this framework uses FPGA as the core of data processing. It uses its powerful parallel processing ability and rich resources to provide a baseband implementation platform for the downlink to ensure communication continuity, stability, and reliability.

关键词： Time-frequency analysis Satellites Protocols Computer architecture Downlink Data processing Stability analysis

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processing in Memory Assisted MEC 3C Resource Allocation for Computation Offloading 20th

Processing in Memory Assisted MEC 3C Resource Allocation for...

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20th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Yang, Yang Chang, Xiaolin Jia, Ziye Han, Zhu Han, Zhen Beijing Jiaotong Univ Beijing Key Lab Secur & Privacy Intelligent Trans Beijing Peoples R China Xidian Univ Informat Sci Inst State Key Lab ISN Xian Peoples R China Univ Houston Dept Elect & Comp Engn Houston TX USA

ISBN: (纸本)9783030602451;9783030602444

the improvement of Internet of things (IoT) applications has led to a substantial increase in the number of multiple resources of computation, communication, and caching (3C). the fifth generation (5G) and multi-access edge computing (MEC) are promising to enhance the computation offloading of IoT applications with high performance and reliability. According to resource-consuming preferences, IoT applications can be divided into computation-hungry applications and memory-hungry applications. To deal with the computation-hungry applications, Graphics processing Units (GPUs) are increasingly used to process simple computation tasks. Meanwhile, the running of memory-hungry applications is accompanied by massive data transfers between processing core and memory. these transfers can result in significant energy and performance costs. processing in memory (PIM) is a computing paradigm that avoids most data movement costs by performing a part of the computations directly in the memory. In this paper, we focus on offloading computation tasks in MEC that require 3C resources with high efficiency and low energy consumption considering latency and resilience constraints in a PIM-assisted multi-core (PAMC) architecture of physical machines (PMs). We formulate an optimization problem to minimize the total weighted resource costs and energy consumption. We also present an algorithm based on the column generation to solve the problem. Simulation results demonstrate that the proposed PAMC architecture can achieve good results in terms of energy consumption and resources utilization in comparison with the traditional PMs' architecture with the same resources.

关键词： Column generation Computation offloading GPU Multi-access edge computing processing in memory

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Local partition subdivision algorithm for approximate nearest neighbor query 7

Local partition subdivision algorithm for approximate neares...

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7th international conference on Information Science and Control Engineering, ICISCE 2020

作者： Dong, Penghui Yang, Yan Heilongjiang University School of Computer Science and Technology Harbin China Heilongjiang Province Key Laboratory of Database and Parallel Computing Harbin China

ISBN: (纸本)9781728164069

this paper solves the problem of approximate nearest neighbor queries on high-dimensional large data sets. the two most representative methods to solve the approximate nearest neighbor query problem on high-dimensional and large-scale data sets are based on inverted multi-index and based on inverted index. the query algorithm based on the inverted multi-index requires frequent access operations to the memory, which causes more waste of resources than the query operation based on the distance order. Traditional query algorithms based on inverted indexes need to divide the entire feature space into a large number of regions to ensure the accuracy of query results when solving the problem of high-dimensional large data sets, so a large amount of space resources are required. Based on the inverted index, a query algorithm is proposed. through the subdivision process of Voronoi Cells that are initially divided into part of the original data set, the purpose is to significantly improve the high-dimensional data set without dividing a large number of regions. On the query performance, and avoid frequent access operations to the random access memory. theoretical analysis and experimental results show that the proposed method not only effectively improves the query processing efficiency, but also ensures the accuracy of the query. © 2020 IEEE.

关键词： Nearest neighbor search

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Design and Implementation of Area-Power Efficient Generic Modular Adder using Flagged Prefix Addition Approach

Design and Implementation of Area-Power Efficient Generic Mo...

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international conference on Signal processing and Communication (ICSC)

作者： Tukur Gupta Shamim Akhter Jaypee Institute of Information Technology Noida India

ISBN: (纸本)9781665427401

Modular adders are employed in the implementation of multipliers, reverse converters, digital signal processors, cryptography and other various residue number system applications. this paper proposes novel adder architecture for moduli of the form 2 n -K where K is any integer in the range of 3 ≤ K ≤ 2 n -1. the Proposed architecture uses Sklansky parallel prefix adder (PPA) in the first stage adder along with the flagged prefix addition technique in the second stage. Use of flagged prefix addition approach significantly reduces the area and power dissipation when compared with published work. Synthesis is done using 90 nm SAED generic library on Synopsys Design Compiler tool and VHDL is used to model the structures under investigation over an input bit range of 7 ≤ n ≤ 15. Reduction up to 42.5% is obtained in the area-power product of the proposed modular adder structure when compared to earlier presented work.

关键词： VHDL Digital signal processors Signal processing Libraries Power dissipation Cryptography Adders

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Design and Analysis of Programming Platform for Accelerated GPU-Like architectures 2020

Design and Analysis of Programming Platform for Accelerated ...

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28th international conference on Real-Time Networks and Systems (RTNS)

作者： Zahaf, Houssam-Eddine Lipari, Giuseppe Lille Univ CRIStAL Lille France

ISBN: (纸本)9781450375931

Many recent computing platforms combine CPUs with different types of accelerators such as Graphical processing Units (GPUs), to cope with the increasing computation needs of complex real-time applications. However, most hardware accelerators have not been designed to provide predictable timing-behavior to support real-time tasks. Moreover, they do not provide efficient preemption mechanisms. In this work, we present the design of a software library to program and execute real-time tasks onto hardware accelerators (e.g. GPUs) that exhibit limited-preemption capabilities with variables costs. the library provides: 1) parallel execution for real-time applications within the same accelerator;2) the choice of different partitioned scheduling algorithms (FP, EDF, Gang-EDF);3) support for (limited) task preemption. We describe a user space implementation of the library as a proof of concept. We also present a schedulability analysis for real-time tasks programmed using this platform, in particular for partitioned EDF and GANG-EDF. the effectiveness of the proposed scheduling strategies and their analyses is demonstrated through 1) actual measurements on a GPU platform, and 2) through synthetic task sets.

关键词： Program processors

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