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Experimental Study on Reducing the Oscillations of a Cable-Suspended parallel Robot for Video Capturing Purposes using Simulated Annealing and Path Planning

Experimental Study on Reducing the Oscillations of a Cable-S...

引用

international conference of Signal processing and Intelligent Systems (ICSPIS)

作者： Mohammad Ghanatian Mohammad Reza Hairi Yazdi Mehdi Tale Masouleh Human and Robot Interaction Laboratory School of Mechanical Engineering University of Tehran Tehran Iran School of Mechanical Engineering University of Tehran Tehran Iran Human and Robot Interaction Laboratory School of Electrical and Computer Engineering University of Tehran Tehran Iran

ISBN: (纸本)9781665409391

this paper aims to smoothen the movements of an under-constrained cable-suspended parallel robot which carries a camera for video capturing purposes, especially for video capturing of football games. this goal is achieved by means of an accurate while simple PID controller optimized by the Simulated Annealing algorithm and implemented on the joint space. Moreover, a planning strategy is considered for the joint space trajectory of the robot which guarantees the zero jerk, acceleration, and velocity at the start and the end of motions. On this regard, a septic function for each joint of the robot is considered and the corresponding boundary conditions are applied to the function to make the end-effector movements less oscillatory. this method is implemented and tested on an experimental setup while the end-effector oscillation data is recorded using an IMU sensor attached to the end-effector of the robot. Applying frequency analysis on the oscillatory data of the end-effector reveals that this simple method, on average, resulted in a 33.8% reduction in the average amplitude of the end-effector oscillations. Moreover, the maximum joint space error was decreased by 76.68% when using septic joint profile compared to the ordinary linear Cartesian trajectory planning approach. Upon applying the proposed strategy, the error of the controller has been reduced by 92.26% with respect to the previous research performed on this experimental setup. Without requiring any knowledge on the dynamic model of the robot or the natural frequencies of the end-effector or using any complex controller, this method significantly increased the smoothness and accuracy of the robot movements. the proposed method can be regarded as a definitive asset when this robot is used for video capturing purposes.

关键词： Vibrations parallel robots Trajectory planning Simulated annealing Games Aerospace electronics End effectors

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ASIC Implementation of Fixed-Point Iterative, parallel, and Pipeline CORDIC Algorithm 8th

ASIC Implementation of Fixed-Point Iterative, Parallel, and ...

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8th international conference on Soft Computing for Problem Solving (SocProS)

作者： Jyothi, Grande Naga Debanjan, Kundu Anusha, Gorantla VIT Univ Vellore Tamil Nadu India GCT Coimbatore Coimbatore Tamil Nadu India

ISBN: (纸本)9789811500350;9789811500343

In this paper, we proposed a Coordinate Rotation Digital Computer (CORDIC) algorithm for efficient hardware implementation of mathematical functions which can be carried out in a wide variety of ways for many digital signal processing applications. the CORDIC is a single unified algorithm for calculating many elementary functions such as trigonometric, hyperbolic, logarithmic function, exponential functions, multiplication, division, and so on. In this paper, a novel low power, low area, and high throughput fixed-point CORDIC algorithms are proposed. the standard CORDIC is also implemented for comparing the synthesis results. the proposed architecture scaling has been done using low area and low-power Scale Factor Correction Unit (SFCU). A low ADP SQRT-CSLA based ADD/SUB unit is proposed to overcomed the disadvantages of the basic ADD/SUB unit used in the standard CORDIC. the ROM lookup table size is also reduced to half. Extensive simulations are performed to verify the functionality. the standard and proposed CORDIC architectures are simulated in cadence NC launch and synthesized in cadence RC tool using TSMC GPDK 45 nm technology and area, power, and delay are calculated. the area and power consumption of the proposed CORDIC architecture are less when compared with standard CORDIC design.

关键词： CORDIC algorithm Pipeline parallel Digital signal processing

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PPBT: A High Performance parallel Search Tree

PPBT: A High Performance Parallel Search Tree

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international conference on High Performance Computing

作者： Jiawen Guan Rui Fan ShanghaiTech University Shanghai China

ISBN: (纸本)9781665410175

Search trees are one of the most important and widely used data structures, and parallelization is an effective method to improve their performance. However, many existing parallel search trees incur high synchronization costs and low memory I/O efficiency, which limits their performance. We propose PPBT, a batched parallel search tree which minimizes synchronization by partitioning the tree using novel algorithms and minimizing I/O cost using buffering. We give a new sequential algorithm for batch processing on search trees with optimal I/O efficiency for insert and delete operations, and also present a fast parallel algorithm for joining disjoint search trees. We show experimentally that PPBT is over 6×faster than the state-of-the-art parallel tree in [1] and over 40× faster than the concurrent search tree in [7], and achieves 21×speedup using 32 threads. PPBT's throughput on searches is lower due to reduced opportunities for buffering, but is still 1.3 × that of [1]. In addition, PPBT has good response times for searches, for example completing 100K searches in under 1 ms in a tree with 10M elements.

关键词： Costs Scalability Instruction sets High performance computing Memory management throughput Partitioning algorithms

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A High Energy Efficiency and Low Resource Consumption FPGA Accelerator for Convolutional Neural Network

A High Energy Efficiency and Low Resource Consumption FPGA A...

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international conference on Computer and Communications (ICCC)

作者： Jianwei Zhang Houjia Cai Jinghu Li Liaoning Key Lab of Integrated Circuit and Biomedical Electronic System School of Biomedical Engineering Dalian University of Technology Dalian China College of Computer and Information Sciences Fujian Agriculture and Forestry University Fuzhou China

ISBN: (纸本)9781665409513

With the rapid development of convolutional neural networks (CNN), the design of hardware accelerators for CNN calculations has become a major focus of current research. However, power consumption and resource consumption are two main limits for the application of CNN hardware accelerators. In response to these problems, a FPGA-based implementation of a CNN hardware accelerator with high energy efficiency and low resource consumption is proposed. the implementation includes zero padding, convolution, batch normalization, ReLU6, and MaxPooling. the computing performance of the network is improved by using pipeline design and layer fusion. the LeNet-5 network is to test the implementation on the Xilinx Virtex VC-707 FPGA board. the experimental result shows that when inferring the MNIST test set, the energy efficiency is 843.91 times and 228.35 times that of the CPU and GPU, respectively.

关键词： Power demand Convolution Pipelines parallel processing Energy efficiency Table lookup Convolutional neural networks

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Performance Analysis of parallel FIR Digital Filter Based on Even Symmetric Fast FIR Algorithm using Different Adders

Performance Analysis of Parallel FIR Digital Filter Based on...

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international conference of Electronics, Communication and Aerospace Technology (ICECA)

作者： S Narendran B T Geetha Institute of Electronics and Communication Engineering Saveetha School of Engineering SIMATS Chennai India

ISBN: (纸本)9781665435253

the ultimate goal of the research work is to analyze the performance of FIR filter designed based on FFA algorithm. the proposed structure aims at area-optimized adders which are designed for symmetric coefficient that reduces hardware cost in the design with a constrain that the filter tap is of even order. Area analysis of silicon chip is performed using different adders like Ripple Carry Adder (RCA), Carry Look-Ahead Adder (CLA) and Conditional Sum Adder (COS). Performance analysis report for a 3 parallel 96-tap filter is considered based on the above adder, where the RCA requires less area utilization compared to other three adders. the symmetric convolution-based RCA Fast FIR Algorithm (FFA) structure requires only 896 slices whereas COS requires 1024 slices and CLA requires 960 slices. For higher-order, FIR filter structure of 1024 or higher taps, the savings in the area utilization for RCA based FFA is approximately 10% and 15% compared to CLA and COS basedFFA respectively because COS requires more hardware building blocks. the RCA based FFA increases the latency by approximately 9% and 7% compared to CLA and COS based FFA respectively, and there will be a trade-off.

关键词： Costs Finite impulse response filters Signal processing algorithms Digital signal processing Filtering algorithms Approximation algorithms Hardware

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Pipeline Architecture for N==K*2L Bit Modular ALU: Case Study between Current Generation Computing and Vedic Computing

Pipeline Architecture for N==K*2L Bit Modular ALU: Case Stud...

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international conference for Convergence of Technology (I2CT)

作者： G.N. Chiranjeevi Subhash Kulkarni Department of Electronics and Communication Engineering PESIT-Bangalore South Campus Bangalore Affiliated to Visvesvaraya Technological University Belagavi Karnataka India

ISBN: (纸本)9781728188768;9781728188775

this paper describes a design architecture that performs mathematical operations using Vedic sutra for upward compatibility in pipeline manner. In spite of increasing the area, performance and reducing power, Vedic architecture have observed to be inherently compatible with higher efficiency for pipeline architecture. However Vedic architecture leads to additional flexibility starting from 2-bit base modules to 8-bit modules (L=1,2,3) and pipeline can be compactable to any base modules for any given length. Many researchers proposed arithmetic algorithms at simulation level using vedic sutra. these algorithm have been evaluated with better performance, area and speed. the literature has been widely found to be towards individual arithmetical operators like multiplier, square and cube and so on. A consolidated computing architecture, especially N-bit ALU is yet be realized Generalized N-bit ALU, can always be realized using pipeline modular architecture. the proposition is on realizing N-bit using `2^L, as base modules using `K' modules in pipelining. the authors have extensively verified modular architecture for 4-Bit modules for 16 bit and 32 bit pipelined operations. Individually multiplication using Urdhva Tiryakbhyam, division using Dhwajanka sutra, square using Dwandwayoga sutra. MAC unit which involves multiplication algorithms used in FFT and IFFT using sutras of Vedic mathematics and it is possible to achieve reduce version interms of speed and delay, compared to different generations of ALU the authors are now exploring N-bit ALU architecture FPGA implementation using Vedic sutras with flexible modular pipeline architecture and mainly targeted for Digital Signal processing applications.

关键词： Computational modeling Signal processing algorithms Process control Computer architecture Digital signal processing parallel architectures Delays

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CA-Market: A Partially Categorical AnnotatingApproach Based on Market1501 Dataset for Attribute Detection

CA-Market: A Partially Categorical AnnotatingApproach Based ...

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international conference of Signal processing and Intelligent Systems (ICSPIS)

作者： Hossein Bodaghi Shayan Samiee Mehdi Tale Masoulehe Ahmad Kalhor Human and Robot Interaction Laboratory University of Tehran Tehran Iran

ISBN: (纸本)9781665409391

In this paper, a new partial categorical attributes dataset (CA-Market) based on images of the Market1501 dataset has been introduced, for the sake of improving the attribute detection task. Most attributes detection datasets (human appearance features detection) are not partially categorical and do not properly take into account the inner classes diversity. Increasing the diversity of inner parts (gender, head, upper-body clothes, lower-body clothes, bags, shoes, and colors) before annotating can ease the decision-making process by dividing labels into individual categories. CA-Market contains 46 binary attributes in 10 parts from head to foot and their colors which are annotated in image-level. For example, the attributes of the leg part are skirts, shorts, and pants which are carefully chosen to be categorized for a classification task. In this research, the effect of the labeling approach is studied. Hence, a common classification method is used and only datasets or baselines are changed for comparisons. Baselines are based on Omni-Scale, Resnet50, and Hydra-Plus architectures to compare the CA-Market1501 dataset with the Market1501 attribute dataset in the same setting. CA-Market demonstrates a new representation of data as a part-based format which can gain better results. this approach, without adding any extra modules, achieved a significant enhancement. For instance, accuracy in the vectorized format is over 92%, in the categorized is over 90% which shows the effectiveness of part-based attribute annotating. Also, hair, backpack, upper color, and lower color as the common attributes between Market1501-attribute and CA-Market datasets are achieved 90.26, 88.04, 94.55, and 94.18 classification accuracy which can outperform existing state-of- the-art approaches.

关键词： Hair Measurement Legged locomotion Head Image color analysis Signal processing Labeling

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Unfair Scheduling Patterns in NUMA architectures 28

Unfair Scheduling Patterns in NUMA Architectures

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28th international conference on parallel architectures and Compilation Techniques (PACT)

作者： Ben-David, Naama Scully, Ziv Blelloch, Guy E. Carnegie Mellon Univ Pittsburgh PA 15213 USA

ISBN: (纸本)9781728136134

Lock-free algorithms are typically designed and analyzed with adversarial scheduling in mind. However, on real hardware, lock-free algorithms perform much better than the adversarial assumption predicts, suggesting that adversarial scheduling is unrealistic. In pursuit of more realistic analyses, recent work has studied lock-free algorithms under gentler scheduling models. this begs the question: what concurrent scheduling models are realistic? this issue is complicated by the intricacies of modern hardware, such as cache coherence protocols and non-uniform memory access (NUMA). In this paper, we thoroughly investigate concurrent scheduling on real hardware. To do so, we introduce Severus, a new benchmarking tool that allows the user to specify a lock-free workload in terms of the locations accessed and the cores participating. Severus measures the performance of the workload and logs enough information to reconstruct an execution trace. We demonstrate Severus's capabilities by uncovering the scheduling details of two NUMA machines with different microarchitectures: one AMD Opteron 6278 machine, and one Intel Xeon CPU E7-8867 v4 machine. We show that the two architectures yield very different schedules, but both exhibit unfair executions that skew toward remote nodes in contended workloads.

关键词： Schedules Scheduling Instruction sets Prediction algorithms Hardware Benchmark testing Coherence

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Numerical Implementation of a Wideband Chaotic Light Based Ring-and-Spur Long-Reach Passive Optical Network: architectures and Real-Time Secure Communications

Numerical Implementation of a Wideband Chaotic Light Based R...

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7th international conference on Communications, Signal processing, and Systems (CSPS)

作者： Dou, Xinyu Yin, Hongxi Wu, Bin Dalian Maritime Univ Sch Informat Sci & Technol Dalian 116026 Liaoning Peoples R China Dalian Univ Technol Sch Informat & Commun Engn Lab Opt Commun & Photon Technol Dalian 116023 Liaoning Peoples R China

ISBN: (纸本)9789811365089;9789811365072

In this paper, a wideband chaotic light based ring-and-spur longreach passive optical network (ring-and-spur LR-PON) is proposed and numerically demonstrated. the bidirectional long-haul secure communication between the optical line terminal (OLT) and the optical network unit (ONU) is realized, in which the bandwidth of the chaos carrier is more than 20 GHz. As a result, the data rate can reach up to 10 Gb/s for each wavelength channel. the proposed network has potential practical values, owing to its advantages such as providing a higher bit rate, achieving a higher level of real-time security, survivability, etc.

关键词： Fiber optics communications Chaos Ring-and-spur LR-PON Real-time security

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parallel Stateful Logic in RRAM: theoretical Analysis and Arithmetic Design 30

Parallel Stateful Logic in RRAM: Theoretical Analysis and Ar...

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30th IEEE international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Wang, Feng Luo, Guojie Sun, Guangyu Zhang, Jiaxi Huang, Peng Kang, Jinfeng Peking Univ Ctr Energy Efficient Comp & Applicat Beijing Peoples R China Peking Univ Inst Microelect Beijing Peoples R China

ISBN: (纸本)9781728116013

processing-in-memory (PIM) provides massive parallelism with high energy efficiency and becomes a promising solution to the "memory wall" problem. Recently, the emerging metal-oxide resistive random access memory (RRAM) has shown its potential to design a PIM architecture. Several stateful logic operations, e.g., NOR and NAND, can be executed in parallel in an RRAM crossbar. Although previous works have designed some algorithms using the stateful logic, it is still under exploration how to fully exploit its potential high parallelism and design an asymptotically fast algorithm for a given function. In this work, we theoretically analyze the parallelism in an RRAM crossbar and design several asymptotically optimal arithmetic algorithms. In detail, we first propose the Single Instruction Multiple Lines (SIML) model to unify the stateful logic families and prove three lower bounds on the time complexity of a parallel RRAM algorithm. then, we design three algorithms for integer addition functions with the stateful logic, guided by the lower bound analysis. All of them reach the time complexity lower bound. Finally, We make two extensions of the integer addition algorithms, supporting multiplication functions by decomposing them to additions and supporting the flex-point data type by proposing an exponent and mantissa update flow. Experimental evaluation shows that our integer algorithms achieves a speedup up to 13.79x over the previous RRAM algorithms. Our flex-point implementation achieves a 26.60x speedup and saves 73.68% energy compared to an ARM.

关键词： Time complexity Computer architecture parallel processing Computational modeling Resistance Switches Random access memory

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