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parallel Searching on Biological Networks 27

Parallel Searching on Biological Networks

引用

27th Euromicro international conference on parallel, Distributed and Network-Based processing (PDP)

作者： Bombieri, Nicola Bonnici, Vincenzo Giugno, Rosalba Univ Verona Dipartimento Informat Strata Grazie 15 I-37134 Verona Italy

ISBN: (纸本)9781728116440

Software applications for biological networks analysis rely on graphs to model the structure interactions. A great part of them requires searching for subgraphs in a target graph or in collections of graphs. Even though very efficient algorithms have been defined to solve such a subgraph isomorphisms problem, the complexity of current real biological networks make their sequential execution time prohibitive. On the other hand, parallel architectures, from multi-core to many-core, have become pervasive to deal with the problem of the data size. Nevertheless, the sequential nature of the graph searching algorithms makes their implementation for parallel architectures very challenging. this paper presents three different parallel solutions for the graph searching problem. the first two target the exact search for multi-core CPUs and many-core GPUs, respectively. the third one targets the approximate search for GPUs, which handles node, edge, and node label mismatches. the paper shows how different techniques have been developed in all the solutions to reduce the search space complexity. the paper shows the performance of the proposed solutions on representative biological networks containing antiviral chemical compounds and protein interactions networks.

关键词： Biology Search problems Complexity theory Graphics processing units Indexes Topology

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An FPGA-Based Balanced and High-Efficiency Two-Dimensional Data Access Technology for Real-Time Spaceborne SAR

An FPGA-Based Balanced and High-Efficiency Two-Dimensional D...

引用

7th international conference on Communications, Signal processing, and Systems (CSPS)

作者： Sun, Tianyuan Li, Bingyi Liu, Xiaoning Xie, Yizhuang Beijing Inst Technol Sch Informat & Elect Radar Res Lab Beijing 100081 Peoples R China Beijing Key Lab Embedded Real Time Informat Proc Beijing 100081 Peoples R China

ISBN: (纸本)9789811365089;9789811365072

With the development of satellite load and very large scale integrated (VLSI) circuit technology, spaceborne real-time synthetic aperture radar (SAR) imaging systems have become a solution for rapid response to hazards. through analyzing the algorithm pipeline flow as well as introducing the storage-computation model, a balanced and high-efficiency 2-D data access technology based on cross-mapping data storage method has been achieved to suit the large point processing for real-time spaceborne SAR system. A proto-type based on NetFPGA-SUME board with Xilinx XC7VX690T is given to verify the performance of the proposed design. Taking Stripmap SAR imaging of 16384 * 16384 granularity raw data (5 m resolution, 25 km width) as an example, the imaging based on chirp scaling algorithm takes 6.63 s, which is better than some other real-time processing methods.

关键词： SAR Real-time processing FPGA parallel accelerating component

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Parameter Filtering Method with Circular Update for Deep Neural Network parallel Training

Parameter Filtering Method with Circular Update for Deep Neu...

引用

international conference on Information Science and Control Engineering (ICISCE)

作者： Gao Haoye Xiao Nanfeng School of Computer Science and Engineering South China University of Technology Guangzhou China

this paper proposes a parameter filtering circular update algorithm, which provides an efficient solution for parallel training of deep neural networks as the scale of deep neural networks continues to expand. the parameter filtering circular update algorithm filters a large number of redundant unimportant parameters in the deep neural network training process by setting the importance threshold, and in an iteration process, the parameters of each node are synchronized through the circular update algorithm. the parameter filtering circular update algorithm compresses the training parameters of the DNN, and greatly reduces the overhead caused by the communication between each node and the parameter server in the synchronous parallel training. Experiments show that the parameter filtering circular update algorithm can improve the parallel training speed of the DNNs without losing the prediction accuracy, and the GPU utilization rate on each computing node is higher than that of the general synchronous training method.

关键词： Training Deep learning Information science Filtering Graphics processing units Filtering algorithms Prediction algorithms

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On the turing completeness of modern neural network architectures 7

On the turing completeness of modern neural network architec...

引用

7th international conference on Learning Representations, ICLR 2019

作者： Pérez, Jorge Marinković, Javier Barceló, Pablo Department of Computer Science Universidad de Chile IMFD Chile Chile

Alternatives to recurrent neural networks, in particular, architectures based on attention or convolutions, have been gaining momentum for processing input sequences. In spite of their relevance, the computational properties of these alternatives have not yet been fully explored. We study the computational power of two of the most paradigmatic architectures exemplifying these mechanisms: the Transformer (Vaswani et al., 2017) and the Neural GPU (Kaiser & Sutskever, 2016). We show both models to be Turing complete exclusively based on their capacity to compute and access internal dense representations of the data. In particular, neither the Transformer nor the Neural GPU requires access to an external memory to become Turing complete. Our study also reveals some minimal sets of elements needed to obtain these completeness results. © 7th international conference on Learning Representations, ICLR 2019. All Rights Reserved.

关键词： Graphics processing unit

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DF-PLSTM-FCN: A Method for Unmanned Driving Based on Dual-Fusions and parallel LSTM-FCN 27th

DF-PLSTM-FCN: A Method for Unmanned Driving Based on Dual-Fu...

引用

27th international conference on Neural Information processing

作者： Wei, Meng Fu, Yuchen Zhong, Shan Li, Zicheng Soochow Univ Sch Comp Sci & Technol Suzhou 215000 Jiangsu Peoples R China Changshu Inst Technol Sch Comp Sci & Engn Changshu 215500 Jiangsu Peoples R China

ISBN: (纸本)9783030638290;9783030638306

Learning algorithms are increasingly being applied to behavioral decision systems for unmanned vehicles. In multi-source road environments, it is one of the key technologies to solve the decision-making problem of driverless vehicles. this paper proposes a parallel network, called DF-PLSTM-FCN, which is composed of LSTM-FCN-variant and LSTM-FCN. As an end-to-end model, it will jointly learn a mapping from the visual state and previous driving data of the vehicle to the specific behavior. Different from LSTM-FCN, LSTM-FCN-variant provides more discernible features for the current vehicle by introducing dual feature fusions. Furthermore, decision fusion is adopted to fuse the decisions made by LSTM-FCN-variant and LSTM-FCN. the parallel network structure with dual fusion on both features and decisions can take advantage of the two different networks to improve the prediction for the decision, without the significant increase in computation. Compared with other deep-learning-based models, our experiment presents competitive results on the large-scale driving dataset BDDV.

关键词： Unmanned driving Decision-making Feature fusion Decision fusion

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An Encoder-Decoder Network with Residual Convolution for Leukocyte Image Segmentation 7

An Encoder-Decoder Network with Residual Convolution for Leu...

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7th international conference on Information Science and Control Engineering, ICISCE 2020

作者： Chen, Yuanyuan Teng, Shenghua Li, Zuoyong Zhang, Fuquan Minjiang University Fujian Provincial Key Laboratory of Information Processing and Intelligent Control College of Computer and Control Engineering Fuzhou350121 China Shandong University of Science and Technology College of Electronics and Information Engineering Qingdao266590 China

ISBN: (纸本)9781728164069

the appearance analysis and counting of peripheral blood leukocytes can assist the diagnosis of blood diseases such as leukemia. therefore, it is necessary to automatically extract leukocytes from blood smear images. In this paper, we propose an end-to-end peripheral blood leukocyte image segmentation method based on fully convolutional neural network, which can not only encode multi-scale contextual information, but also capture clear boundary information through decoding. Specifically, the proposed method first utilizes the context-aware feature encoder with residual convolutions to extract a set of multi-scale features. then, a refinement module of parallel dilated convolutions with multiple dilation rates for expanding the receptive field of the feature maps is introduced to aggregate contextual information. Finally, clear prediction results are reconstructed by the context-aware feature decoder and skip connections. We demonstrate the effectiveness of the proposed method on two publicly available datasets. © 2020 IEEE.

关键词： Convolution

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the Passive DOA Estimation by Virtual Time Reversal on FPGA

The Passive DOA Estimation by Virtual Time Reversal on FPGA

引用

international conference on Information Science and Control Engineering (ICISCE)

作者： Zhixin Yu Yongqing Fu College of Information and Communication Engineering Harbin Engineering University Harbin China

the Virtual Time Reversal algorithm has the advantages of low computational complexity and high accuracy in low signal-to-noise ratio, so it is easy to implement in hardware engineering. the parallel design of FPGA can greatly improve the speed of direction finding system and satisfy the real-time direction finding. the paper adopts Virtex-7 FPGA of Xilinx Company with Verilog-HDL to program the design of Passive DOA Estimation by Virtual Time Reversal (PVTR-DOA). Firstly, according to the principle of Virtual Time Reversal algorithm, a parallel processing scheme is proposed. this design establishes the algorithm module through Vivado software platform, and uses package IP tool to package the algorithm module into a custom IP core. then, the data to be tested in DDR3 and the custom IP core are moved through DMA data interaction mode for signal processing. the FPGA design uses MicroBlaze core to implant C code on SDK platform to control the embedded system. Finally, the effectiveness and real-time direction finding of the hardware design are verified by the experimental results.

关键词： Embedded systems Direction-of-arrival estimation Software algorithms Signal processing algorithms Estimation Real-time systems Hardware

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Exploiting Vector processing in Dynamic Binary Translation 19

Exploiting Vector Processing in Dynamic Binary Translation

引用

48th international conference on parallel processing (ICPP)

作者： Lin, Chih-Min Fu, Sheng-Yu Hong, Ding-Yong Liu, Yu-Ping Wu, Jan-Jan Hsu, Wei-Chung Natl Taiwan Univ Taipei Taiwan Acad Sinica Taipei Taiwan

ISBN: (纸本)9781450362955

Auto vectorization techniques have been adopted by compilers to exploit data-level parallelism in parallel processing for decades. However, since processor architectures have kept enhancing with new features to improve vector/SIMD performance, legacy application binaries failed to fully exploit new vector/SIMD capabilities in modern architectures. For example, legacy ARMv7 binaries cannot benefit from ARMv8 SIMD double precision capability, and legacy x86 binaries cannot enjoy the power of AVX-512 extensions. In this paper, we study the fundamental issues involved in cross-ISA Dynamic Binary Translation (DBT) to convert non-vectorized loops to vector/SIMD forms to achieve greater computation throughput available in newer processor architectures. the key idea is to recover critical loop information from those application binaries in order to carry out vectorization at runtime. Experiment results show that our approach achieves an average speedup of 1.42x compared to ARMv7 native run across various benchmarks in an ARMv7-to-ARMv8 dynamic binary translation system.

关键词： Dynamic Binary Translation Virtual Register Promotion SIMD/Vector Auto Vectorization

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High throughput Hardware for Hoeffding Tree Algorithm with Adaptive Naive Bayes Predictor

High Throughput Hardware for Hoeffding Tree Algorithm with A...

引用

international conference for Convergence of Technology (I2CT)

作者： Ashin Antony Devi A Kuruvilla Varghese Indian Institute Of Science Bangalore India

Hoeffding tree algorithm is a popular online decision tree algorithm capable of learning from huge data streams. the algorithm involves complex time consuming computations in the leaves of the tree for each data instance. these computations involve a lot of parallelisms which can be exploited and implemented in a field programmable gate array to achieve speedup. this paper presents a hardware accelerator for Hoeffding tree algorithm with adaptive naive bayes predictor in the leaves. the proposed system is capable of accelerating data streams with both nominal and numeric attributes using minimum hardware resources for huge datasets. It is implemented on a Xilinx VC707 board based on Virtex-7 XC7VX485T field programmable gate array. the implemented system is about 9x faster than StreamDm(C++), a well known reference software implementation for the standard forest cover type dataset.

关键词： Vegetation parallel processing Logic gates Prediction algorithms throughput Hardware Table lookup

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Controlled Asynchronous GVT: Accelerating parallel Discrete Event Simulation on Many-Core Clusters 19

Controlled Asynchronous GVT: Accelerating Parallel Discrete ...

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48th international conference on parallel processing (ICPP)

作者： Eker, Ali Williams, Barry Chiu, Kenneth Ponomarev, Dmitry Binghamton Univ Binghamton NY 13902 USA

ISBN: (纸本)9781450362955

In this paper, we investigate the performance of parallel Discrete Event Simulation ( PDES) on a cluster of many-core Intel KNL processors. Specifically, we analyze the impact of different Global Virtual Time (GVT) algorithms in this environment and contribute three significant results. First, we show that it is essential to isolate the thread performing MPI communications from the task of processing simulation events, otherwise the simulation is significantly imbalanced and performs poorly. this applies to both synchronous and asynchronous GVT algorithms. Second, we demonstrate that synchronous GVT algorithm based on barrier synchronization is a better choice for communication-dominated models, while asynchronous GVT based on Mattern's algorithm performs better for computation-dominated scenarios. third, we propose Controlled Asynchronous GVT (CA-GVT) algorithm that selectively adds synchronization to Mattern-style GVT based on simulation conditions. We demonstrate that CA-GVT outperforms both barrier and Mattern's GVT and achieves about 8% performance improvement on mixed computation-communication models. this is a reasonable improvement for a simple modification to a GVT algorithm.

关键词： parallel Discrete Event Simulation Intel Xeon Phi Knights Landing Manycore architectures Performance Global Virtual Time

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