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Generic methodology for the design of parallel algorithms based on pattern languages 9th

Generic methodology for the design of parallel algorithms ba...

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9th international conference on Supercomputing, ISUM 2018

作者： Serrano-Rubio, A. Alejandra Meneses-Viveros, Amilcar Morales-Luna, Guillermo B. Paredes-López, Mireya Computer Science Department Cinvestav-IPN Mexico City Mexico Mathematics Department Cinvestav-IPN Mexico City Mexico

ISBN: (纸本)9783030104474

A parallel system to solve complex computational problems involve multiple instruction, simultaneous flows, communication structures, synchronisation and competition conditions between processes, as well as mapping and balance of workload in each processing unit. the algorithm design and the facilities of processing units will affect the cost-performance ratio of any algorithm. We propose a generic methodology to capture the main characteristics of parallel algorithm design methodologies, and to add the experience of expert programmers through pattern languages. Robust design considering the relations between architectures and programs is a crucial item to implement high-quality parallel algorithms. We aim for a methodology to exploit algorithmic concurrencies and to establish optimal process allocation into processing units, exploring the lowest implementation details. Some basic examples are described, such as the k-means algorithm, to illustrate and to show the effectiveness of our methodology. Our proposal identifies essential design patterns to find models of Data Mining algorithms with string self-adaptive mechanisms for homogeneous and heterogeneous parallel architectures. © Springer Nature Switzerland AG 2019.

关键词： parallel algorithms

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Speeding up CSIDH using parallel computation of isogeny

Speeding up CSIDH using parallel computation of isogeny

引用

international conference of Advanced Informatics: Concept, theory and Application (ICAICTA)

作者： Ganma Kato Koutarou Suzuki Toyohashi University of Technology Toyohashi Aichi Japan

ISBN: (纸本)9781728180397

Isogeny-based cryptography is a promising candidate for post-quantum cryptography. CSIDH is a Diffie-Hellman key exchange protocol based on isogeny with a small public key size and is secure against a quantum computer. However, one of the problems is that it takes a long time to compute the group action corresponding to the secret key. Several efficiency improvements have already been studied, such as the SIMBA technique by Meyer, Campos, and Reith, and the two-point method by Onuki, Aikawa, Yamazaki, and Takagi. In this paper, we propose parallel computation method for the isogeny in CSIDH, which speeds up the computation of the isogeny from O(d) to O(logd), where d = (ℓ-1)/2 and ℓ is the degree of the isogeny.

关键词： Quantum computing Protocols Public key parallel processing Computational efficiency Task analysis Kernel

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Efficient parallel GCD algorithms for Multicore Shared Memory architectures

Efficient Parallel GCD Algorithms for Multicore Shared Memor...

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international conference on Advances in ICT for Emerging Regions

作者： Gihan tharaka Pathirana Sittampalam Sotheeswaran Nagulan Ratnarajah Faculty of Science Eastern University Sri Lanka Faculty of Applied Science Vavuniya Campus of the University of Jaffna Sri Lanka

ISBN: (数字)9781728186559

ISBN: (纸本)9781728186566

the greatest common divisor (GCD) is used for numerous applications in number theory, modular arithmetic, encryption algorithms such as RSA, random number generation, and solving linear Diophantine equations. High-performance algorithms, which are efficiently and accurately find the GCD of two integers and n (>2) integers, are needed in the modern world for many applications in science and engineering. parallel hardware and parallel programming solve such emerging challenges that are not possible in a serial world. Modern desktop and laptop computers are equipped with multicore processors with shared memory architecture. In this paper, we develop novel efficient parallel n integers GCD algorithms for multicore shared memory architecture. the brute force, divide-and-conquer, linear recursive and finding minimum first techniques are adopted in our novel algorithms to reduce the size and the complexity of the n integers GCD problem. Various working models of OpenMP, such as the thread-centric, loop-centric and task-centric models are utilized, which promised a more natural way of exploiting and expressing regular and irregular algorithms. A comprehensive performance analysis applies to prove the efficiency of the proposed algorithms.

关键词： parallel algorithms Task analysis Multicore processing Time complexity Software algorithms Memory architecture Heuristic algorithms

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High Performance Convolutional Neural Network Accelerator Based on Design Space Exploration

High Performance Convolutional Neural Network Accelerator Ba...

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international conference on Information Science and Control Engineering (ICISCE)

作者： Wei Pang Shengli Lu Southeast University Nanjing China

Convolutional neural networks (CNNs) have achieved a wide range of applications in the field of computer vision. However, its large number of parameters and computation limits its deployment in embedded terminals. Designing dedicated CNN accelerators becomes an efficient way to solve the situation. In this paper, a basic access model of systolic accelerator is established to find the optimal design parameters for specific CNN structure. the experiment result shows that $14 \times16$ is the optimum size of processing element array for AlexNet and VGG16, which matches with the design parameters of accelerators with the same architecture.

关键词： Information science Computer vision Power demand Control engineering parallel processing Systolic arrays Energy efficiency

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Multiple algorithms Against Multiple Hardware architectures: Data-Driven Exploration on Deep Convolution Neural Network 16th

Multiple Algorithms Against Multiple Hardware Architectures:...

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16th IFIP WG 10.3 international conference on Network and parallel Computing, NPC 2019

作者： Xu, Chongyang Luan, Zhongzhi Gao, Lan Wang, Rui Zhang, Han Zhang, Lianyi Liu, Yi Qian, Depei Beihang University Beijing China Science and Technology on Special System Simulation Laboratory Beijing Simulation Center Beijing China

ISBN: (纸本)9783030307080

With the rapid development of deep learning (DL), various convolution neural network (CNN) models have been developed. Moreover, to execute different DL workloads efficiently, many accelerators have been proposed. To guide the design of both CNN models and hardware architectures for a high-performance inference system, we choose five types of CNN models and test them on six processors and measure three metrics. With our experiments, we get two observations and conduct two insights for the design of CNN algorithms and hardware architectures. © 2019, IFIP international Federation for Information processing.

关键词： Neural network models

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A Pipeline-Friendly In-place Linear Transformation

A Pipeline-Friendly In-place Linear Transformation

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international conference on Information Science and Control Engineering (ICISCE)

作者： Leilei Yu Sian-Jheng Lin Na Wang School of Cyberspace Security University of Science & Technology of China (USTC) Heifei China School of Cyberspace Security USTC Heifei China

In-place linear transformation has the characteristics of saving memory space. In this paper, based on Gaussian elimination, we propose an in-place linear transformation that is friendly for pipeline computations. the simulations show that the throughput of the proposed algorithm is up to around 60% higher than the prior approach. For larger-scale transformations, the proposed algorithm is comparable in single-thread performance with the math libraries, such as Eigen and MKL, while these libraries do not possess the in-place property.

关键词： Information science Control engineering Computational modeling Pipelines parallel processing throughput Libraries

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Implementation of Area Efficient Pipelined R22SDF FFT Architecture

Implementation of Area Efficient Pipelined R22SDF FFT Archit...

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international conference on Smart Structures and Systems (ICSSS)

作者： C.Ramesh Kumar M.P. Chitra Sathyabama Institute of Science and Technology Chennai India Panimalar Institute of Technology Chennai India

ISBN: (数字)9781728172231

ISBN: (纸本)9781728172286

this paper presents the analysis of various architectures of Low power FFT Processors. FFT is a major building block in DSP and communication system. FFT is an efficient way to implement DFT in a faster manner. Using FFT the number of multiplication and addition order O(N/2log 2 N) and O(Nlog 2 N) are reduced. Conventional FFT has more chip area and delay. Hence pipelined FFT is preferred to overcome the demerits of the conventional processor. this paper reports a detailed study of various FFT architectures and mainly about R2 2 SDF SDF FFT. In this paper, to reduce delay an advanced design of 64-point Pipelined Radix 2 2 Single Path Delay Feedback (R2 2 SDF) FFT architecture has been proposed by using Verilog Hardware Description Language (Verilog HDL). the simulation results has been evaluated by using Modelsim 6.3C and synthesis results are estimated by using Xilinx Planahead 12.4i design tool.

关键词： Delays Program processors Commutators Memory architecture Signal processing algorithms Discrete Fourier transforms

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VLSI architectures for 8 bit data comparators for rank ordering image applications 8

VLSI architectures for 8 bit data comparators for rank order...

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8th IEEE international conference on Communication and Signal processing, ICCSP 2019

作者： Sindhu, E. Vasanth, K. Department of VLSI system Design Vidya Jyothi Institute of Technology Telanagana Hyderabad500075 India Vidya Jyothi Institute of Technology Telangana Hyderabad500075 India

ISBN: (纸本)9781538675953

the main objective of the proposed work is to develop a new Data comparator which gives an economical solution for sorting / Rank ordering networks on the basis of speed, power, and area. the proposed work comprises a design of six different comparators for 8 -bit comparison. the performances of these six different comparators were targeted for XCV1000-4bg560 using Xilinx 7.1i compiler tool using VHDL. It was found that Carry select logic based data comparator requires less area and suitable for reduced area applications. the Conventional bit wise logic based data comparator operated with less delay. Hence this architecture can be used for high speed application. the Twos complement using binary to excess one data converter consumes less power. Hence a twos complement based implementation is suitable for low power implementations. the Different architecture for data comparators were applied on parallel and pipelined architecture of modified shear sorting. these three architectures were compared with other existing median finding architectures. It was found that the CSLA based parallel architecture, CBC based pipelined architecture and 2BEC based pipelined architecture were stand out in area, speed and power when compared with conventional median finding algorithms. © 2019 IEEE.

关键词： Comparators (optical)

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Hardware Deceleration of Kvazaar HEVC Encoder 19th

Hardware Deceleration of Kvazaar HEVC Encoder

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19th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation (SAMOS)

作者： Sainio, Joose Mercat, Alexandre Vanne, Jarno Tampere Univ Tampere Finland

ISBN: (纸本)9783030275624;9783030275617

High Efficiency Video Coding (HEVC) doubles the coding efficiency of the prior Advanced Video Coding (AVC) standard but tackling its huge complexity calls for efficient HEVC codec implementations. the recent advances in Graphics processing Units (GPUs) have made programmable general-purpose GPUs (GPGPUs) a popular option for accelerating various video coding tools. Massively parallel GPU architectures are particularly well suited for hardware-oriented full search (FS) algorithm in HEVC integer motion estimation (IME). this paper analyzes the feasibility of a GPU-accelerated FS implementation in the practical Kvazaar open-source HEVC encoder. According to our evaluations, implementing FS on AMD Radeon RX 480 GPU makes Kvazaar 12.5 times as fast as the respective anchor implemented entirely on an Intel 8-core i7 processor. However, the obtained speed gain is lost when fast IME algorithms are put into use in the anchor. For example, executing the anchor with hexagon-based search (HEXBS) algorithm is almost two times as fast as our GPU-accelerated proposal and the benefit of GPU offloading is reduced to a slight coding gain of 1.2%. Our results show that accelerating IME on a GPU speeds up non-practical encoders due to their enormous inherent complexity but the price paid with practical encoders tends to be too high. Conditional processing schemes of fast IME algorithms can be efficiently executed on processors without any substantial coding loss over that of FS. Nevertheless, we still believe there might be room for exploiting GPU on IME acceleration but GPU-parallelized fast algorithms are needed to get value for additional implementation cost and power budget.

关键词： High Efficiency Video Coding (HEVC) HEVC encoder Graphics processing Unit (GPU) Integer Motion Estimation (IME) Full-Search (FS)

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Design and Verification of High-Speed Radix-2 Butterfly FFT Module for DSP Applications

Design and Verification of High-Speed Radix-2 Butterfly FFT ...

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international conference on Trends in Electronics and Informatics (ICEI)

作者： Utsav Kumar Malviya Government Engineering College Bilaspur India

ISBN: (数字)9781728155180

ISBN: (纸本)9781728155197

Digital signal processing (DSP) processor is a key element of 4th Generation (4G) communication and Fast Fourier Transform (FFT) is an important operation of the modern Digital signal Processor (DSP). this work design an area and speed optimized FFT module for the DSP processor. Real-time computation of signals must meet real-time scenarios and highly requires to make computation faster as possible, hence a fast FFT proposed. Two types of methods can be used for FFT operation: first is Decimation in time (DIT) and second is Decimation in frequency (DIF). the operational speed of these algorithms depends on the multipliers used for computation. Multipliers in the FFT process are the key factor for the speed performance and if multiplier modifies in terms of area and speed overall FFT processor also performance gets an increase. this work design FFT processor with Vedic multiplier and new semi-pipelined Fast Fourier transform (SPFFT) with modified multiplication arrangement gave a provide area optimized hardware architecture. In conventional method, radix-2 2 had been used only for single-path delay feedback architectures. Later with many types of research works radix, 22 was extended to multipath delay commutation (MDC) architectures. this work design is provided for parallel operation of value 16 signal samples, Xilinx Vivado EDA is used for the implementation of this work. for emulation Zynq-7 FPGA board used.

关键词： Adders Random access memory Pipeline processing conferences Market research Informatics Digital signal processing

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