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A Vision System for Shot Tracking and thrown Distance Measurement

A Vision System for Shot Tracking and Thrown Distance Measur...

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international conference on Information Science and Control Engineering (ICISCE)

作者： Huajie Wen Zhiyong Xiao Yutong Li Yuan Xu College of Big Data and Internet Shenzhen Technology University Shenzhen China

this paper presents a vision system for the tracking of the shot and the measure of the thrown distance in a shot put competition. the pan-tilt-zoom (PTZ) camera is used to capture images of the shot and track the shot to the landing position, and the lidar is used to measure the thrown distance once the landing position is determined. A new algorithm based on Hough gradient is developed in order to detect object quickly. the algorithm is further accelerated through GPU parallel computing and implemented on NVIDIA TX2. the control of the system is realized with an onboard arm processor. the system is able to handle video steam of 75 frame per second (FPS), where the image resolution is $640 \times 480$ pixels.

关键词： Information science Laser radar Image resolution Control engineering Machine vision Process control Graphics processing units

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Approximate Sorting Check Node processing in Non-Binary LDPC Decoders

Approximate Sorting Check Node Processing in Non-Binary LDPC...

引用

IEEE international conference on Electronics, Circuits and Systems (ICECS)

作者： Dimitris Chytas Vassilis Paliouras University of Patras Patras Greece

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

this paper proposes the use of parallel approximate sorting networks in Non-Binary LDPC decoders and quantifies their impact in terms of performance and complexity. Motivated by the messages truncation concept of the Extended Min Sum (EMS) algorithm and the reduction it induces on the decoding complexity, we seek for an approximate parallel sorting strategy for the Elementary Check Node (ECN) Unit processing in the EMS algorithm. We quantify the impact of parallel approximate sorting on both error correction decoding performance and hardware complexity. Bubble check sorting methods are compared to proposed parallel approximate sorting techniques in terms of BER vs. noise plots. Furthermore hardware synthesis results are provided to demonstrate the effects of parallel sorting networks on area and throughput. In certain cases of practical interest, a modest degradation of 0.2 dB in coding gain is imposed; however due to proposed parallel approximate sorters, the latency of ECN can be reduced by up to a factor of two or be logarithmic to the input sequence length, in certain architectures. To better illustrate the impact of the proposed techniques, a complete NB-LDPC decoder has been implemented and used for evaluation; it is found that a substantial reduction in the number of clock cycles required per decoding iteration is achieved by the proposed techniques, more than 50% in certain cases.

关键词： Sorting Decoding Complexity theory Parity check codes Approximation algorithms Degradation Signal to noise ratio

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PhD Forum: Towards Embedded Heterogeneous FPGA-GPU Smart Camera architectures for CNN Inference 13

PhD Forum: Towards Embedded Heterogeneous FPGA-GPU Smart Cam...

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13th international conference on Distributed Smart Cameras (ICDSC)

作者： Carballo-Hernandez, Walther Berry, Francois Pelcat, Maxime Arias-Estrada, Miguel Inst Pascal Dept Images Percept Syst & Robot Aubiere France UMR CNRS Inst Natl Sci Appliquees INSA Rennes IETR Dept Images Rennes France INAOE Dept Comp Sci Puebla Mexico

ISBN: (纸本)9781450371896

the success of Deep Learning (DL) algorithms in computer vision tasks have created an on-going demand of dedicated hardware architectures that could keep up with the their required computation and memory complexities. this task is particularly challenging when embedded smart camera platforms have constrained resources such as power consumption, processing Element (PE) and communication. this article describes a heterogeneous system embedding an FPGA and a GPU for executing CNN inference for computer vision applications. the built system addresses some challenges of embedded CNN such as task and data partitioning, and workload balancing. the selected heterogeneous platform embeds an Nvidia (R) Jetson TX2 for the CPU-GPU side and an Intel Altera (R) Cyclone10GX for the FPGA side interconnected by PCIe Gen2 with a MIPI-CSI camera for prototyping. this test environment will be used as a support for future work on a methodology for optimized model partitioning.

关键词： Heterogeneous Computing Edge Computing Internet of things parallel Programming Single Instruction Multiple Data Pipelining Models of Computation and Architecture

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Analysis of relationship between SIMD-processing features used in NVIDIA GPUs and NEC SX-Aurora TSUBASA vector processors 1

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15th international conference on parallel Computing Technologies, PaCT 2019

作者： Afanasyev, Ilya V. Voevodin, Vadim V. Voevodin, Vladimir V. Komatsu, Kazuhiko Kobayashi, Hiroaki Research Computing Center of Moscow State University Moscow119234 Russia Tohoku University SendaiMiyagi980-8579 Japan

ISBN: (数字)9783030256364

ISBN: (纸本)9783030256357

this paper presents comprehensive analysis of main SIMD-processing features and computational characteristics of three high performance architectures: two NVIDIA GPU architectures (of Pascal and Volta generations) and NEC SX-Aurora TSUBASA vector processor. Since both these types of architectures strongly rely on using SIMD-processing features, certain similarities of data-processing principles can be found between them. However, despite having vectorised data-processing included in both NVIDIA GPU and NEC SX-Aurora TSUBASA architectures, vectorisation features of both architectures are implemented in completely different ways. these differences lead to several fundamental restrictions on classes of algorithms which can be efficiently implemented on corresponding platforms. this paper is devoted to the research of the possibility of porting various classes of programs and algorithms among the discussed architectures with a focus on utilising all vectorisation features available. However, without a detailed analysis of similar and different SIMD-processing features in these architectures, it is impossible to approach this problem. the performed analysis allowed us to identify several important examples of typical applications and algorithms. Some of them demonstrated comparable and the others showed different efficiency on NVIDIA GPUs and NEC SX-Aurora TSUBASA vector processors, including reduction operations, programs relying on frequent indirect memory accesses and data-transfers through co-processor interconnect. Moreover, the conducted analysis allows to easily extend this set of examples to approach the problem of automated porting of programs between the reviewed architectures, what we consider as an important direction of our future research. © 2019, Springer Nature Switzerland AG.

关键词： Graphics processing unit

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Proceedings - 7th international conference on Applied Computing and Information Technology, ACIT 2019

Proceedings - 7th International Conference on Applied Comput...

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7th international conference on Applied Computing and Information Technology, ACIT 2019

ISBN: (纸本)9781450371735

the proceedings contain 40 papers. the topic discussed include: wikitheoria: a computational framework for parsimonious sociology theory construction;using pre-trained embeddings to detect the intent of an email;recognition of object hardness from images using a capsule network;transformer design software with parallel processing;design of efficient distribution transformer: a deep learning approach;do virtual reality images provide greater relaxation effects than 2D images?;study on watching system for door-to-door sales detection and risk determination;and study on method of veering correction by vibration transmission in walking support for visually impaired people.

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Reference Point Based Multi-objective Evolutionary Algorithm for DNA Sequence Design 14th

Reference Point Based Multi-objective Evolutionary Algorithm...

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14th international conference on Bio-inspired Computing: theories and Applications, BIC-TA 2019

作者： Zhao, Haozhi Xu, Zhiwei Zhang, Kai School of Computer Science and Technology Wuhan University of Science and Technology WuhanHubei430065 China Hubei Province Key Laboratory of Intelligent Information Processing and Real-Time Industrial System WuhanHubei430065 China

ISBN: (纸本)9789811534140

DNA computing is a parallel computing model based on DNA molecules. High-quality DNA sequences can prevent unwanted hybridization errors in the computation process. the design of DNA molecules can be regarded as a multi-objective optimization problem, which needs to satisfy a variety of conflicting DNA encoding constraints and objectives. In this paper, a novel reference point based multi-objective optimization algorithm is proposed for designing reliable DNA sequences. In order to obtain balance Similarity and H-measure objective values, the reference point strategy is adapted to searching for idea solutions. Firstly, every individual should be assigned a rank value by the non-dominated sort algorithm. Secondly, the crowding distance is replaced by the distance to the reference point for each individual. Lastly, the proposed algorithm is compared with some state-of-the-art DNA sequence design algorithms. the experimental results show our algorithm can provide more reliability DNA sequences than existing sequence design techniques. © 2020, Springer Nature Singapore Pte Ltd.

关键词： Multiobjective optimization

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EMBA: Efficient Memory Bandwidth Allocation to Improve Performance on Intel Commodity Processor 19

EMBA: Efficient Memory Bandwidth Allocation to Improve Perfo...

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48th international conference on parallel processing (ICPP)

作者： Xiang, Yaocheng Ye, Chencheng Wang, Xiaolin Luo, Yingwei Wang, Zhenlin Peking Univ Shenzhen Peoples R China Huazhong Univ Sci & Technol Wuhan Hubei Peoples R China Michigan Technol Univ Houghton MI 49931 USA Peking Univ SECE Shenzhen Key Lab Cloud Comp Technol & Applicat Shenzhen Peoples R China Pengcheng Lab Shenzhen Peoples R China Huazhong Univ Sci & Technol Natl Engn Res Ctr Big Data Technol & Syst Serv Comp Technol & Syst Lab Cluster & Grid Comp LabSch Comp Sci & Technol Wuhan Hubei Peoples R China

ISBN: (纸本)9781450362955

On multi-core processors, contention on shared resources such as the last level cache (LLC) and memory bandwidth may cause serious performance degradation, which makes efficient resource allocation a critical issue in data centers. Intel recently introduces Memory Bandwidth Allocation (MBA) technology on its Xeon scalable processors, which makes it possible to allocate memory bandwidth in a real system. However, how to make the most of MBA to improve system performance remains an open question. In this work, (1) we formulate a quantitative relationship between a program's performance and its LLC occupancy and memory request rate on commodity processors. (2) Guided by the performance formula, we propose a heuristic bound-aware throttling algorithm to improve system performance and (3) we further develop a hierarchical clustering method to improve the algorithm's efficiency. (4) We implement these algorithms in EMBA, a low-overhead dynamic memory bandwidth scheduling system to improve performance on Intel commodity processors. the results show that, when multiple programs run simultaneously on a multi-core processor whose memory bandwidth is saturated, the programs with high memory bandwidth demand usually use bandwidth inefficiently compared with programs with medium memory bandwidth demand from the perspective of CPU performance. By slightly throttling the former's bandwidth, we can significantly improve the performance of the latter. On average, we improve system performance by 36.9% at the expense of 8.6% bandwidth utilization rate.

关键词： Memory bandwidth allocation Multi-core architectures

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New Adiabatic Error Tolerant Adder I architectures

New Adiabatic Error Tolerant Adder I Architectures

引用

international conference on Signal processing and Integrated Networks (SPIN)

作者： Aditya S Kumar Abhishek Wadhwa Neeta Pandey Department of Electronics and Communication Delhi Technological University Delhi India

ISBN: (数字)9781728154756

ISBN: (纸本)9781728154763

this paper proposes two architectures of 16-bit Adiabatic Error Tolerant Adder I (ETA I). the first architecture is based on adaptation of ETA I in Adiabatic domain and is termed as AETA-I. the approximate part in AETA-I uses large number of buffers and its delay dominates the computation time, thus not fully utilizing the benefits of Approximate Computing. the second architecture addresses this issue by modifying AETA-I (META-I), processing propagate and generate bits rather than actual input values. this modification reduces the number of buffers significantly (3.42 times) and culminates into reduction in pipeline depth, power and area. the proposed adders are implemented using Positive Feedback Adiabatic Logic (PEAL) and are validated using 45nm PTM HP technology parameters in Tanner T- Spice™. For a wider comparison, PEAL based 16-bit Kogge Stone Adder (KSA) is also implemented. the proposed MAETA-I architecture has a maximum power savings of 44.94% and 30.33% at 50MHz when compared with Adiabatic KSA and AETA-I respectively.

关键词： Adiabatic Adders Handheld computers Automation Europe Design methodology Communications technology

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parallelization of Variable Rate Decompression through Metadata

Parallelization of Variable Rate Decompression through Metad...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： Lennart Noordsij Steven van der Vlugt Mohamed A. Bamakhrama Zaid Al-Ars Peter Lindstrom ASML Netherlands Synopsys Corporation Netherlands TU Delft Netherlands Lawrence Livermore National Laboratory United States of America

ISBN: (数字)9781728165820

ISBN: (纸本)9781728165837

Data movement has long been identified as the biggest challenge facing modern computer systems' designers. To tackle this challenge, many novel data compression algorithms have been developed. Often variable rate compression algorithms are favored over fixed rate. However, variable rate decompression is difficult to parallelize. Most existing algorithms adopt a single parallelization strategy suited for a particular HW platform. Such an approach fails to harness the parallelism found in diverse modern HW architectures. We propose a parallelization method for tiled variable rate compression algorithms that consists of multiple strategies that can be applied interchangeably. this allows an algorithm to apply the strategy most suitable for a specific HW platform. Our strategies are based on generating metadata during encoding, which is used to parallelize the decoding process. To demonstrate the effectiveness of our strategies, we implement them in a state-of-the-art compression algorithm called ZFP. We show that the strategies suited for multicore CPUs are different from the ones suited for GPUs. On a CPU, we achieve a near optimal decoding speedup and an overhead size which is consistently less than 0.04% of the compressed data size. On a GPU, we achieve average decoding rates of up to 100 GiB/s. Our strategies allow the user to make a trade-off between decoding throughput and metadata size overhead.

关键词： Decoding Metadata Compression algorithms Encoding Data transfer Acceleration Multicore processing

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the Design of Lightweight and Multi parallel CNN Accelerator Based on FPGA 8

The Design of Lightweight and Multi Parallel CNN Accelerator...

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IEEE 8th Joint international Information Technology and Artificial Intelligence conference (ITAIC)

作者： Li Zong-ling Wang Lu-yuan Yu Ji-yang Cheng Bo-wen Hao Liang China Acad Space Technol Beijing Inst Spacecraft Syst Engn Beijing 100094 Peoples R China

ISBN: (纸本)9781538681787

In this paper, a lightweight, parallel computing and storage, high energy efficiency CNN accelerator based on FPGA was designed. According to the characteristics of forward inference structure of deep convolution neural network, the parallel characteristics of convolution operation are analyzed from two aspects of computational efficiency and data reuse rate, and the full parallel pipeline implementation of full connection layer is studied. the accelerator has adopted full parallel pipeline structure to improve the computational efficiency, and making full use of various convolution parallel computing architectures to balance the requirements of computing efficiency, parameters and data load bandwidth, a lightweight and tightly coupled accelerator architecture is designed based on the characteristics of hardware resources such as internal computing, logic and storage in FPGA. In the validation test of open data set based on ImageNet, the accelerator is deployed on Xilinx Virtex7-690T FPGA with 28nm technology, under the working frequency of 200MHz, the maximum number of multiplication and addition operation is 1728 times per cycle, the peak operation rate is 691.2Gops, the energy ratio is 138.24Gops/w. In the end, the classification results are consistent with the processing results using double-precision floating-point data format.

关键词： Convolution neural network MobileNetV2 Model Lightweight parallel compute and storage High energy efficiency ratio FPGA

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