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7th international conference on Emerging Databases - Technologies, Applications, and theory (EDB)

作者： En, Elena Alam, Aftab Khan, Kifayat Ullah Lee, Young-Koo Kyung Hee Univ Dept Comp Sci & Engn Yongin 446701 South Korea

ISBN: (纸本)9789811065200;9789811065194

Large graphs such as social network, web graph, biological network, are complex and facing the challenges of processing and visualization. Motivated by such issues, Taivonen et al. [1] proposed models and sequential algorithms for weighted graph with the intentions to generate a candidate compress graph. the proposed compression algorithm is expensive in terms of computation time because of the sequential process. the weighted graph compression algorithms can be made faster while adopting parallel processing technique. In this paper, we adopt parallel processing technique for weighted graph compression problem while using multi-selection nodes to perform merge-able technique with various graph clustering algorithms to avoid overlapping between nodes from different threads. For the performance evaluation purposes of the proposed method, we carry out series of tests on the real networks. We perform extensive experiments on parallel graph summarization while using different graph clustering algorithms. Our results demonstrate their effectiveness for parallel graph compression on real networks.

关键词： Weighted graph Network Graph compression Graph clustering parallel processing Graph mining

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Creation of a multinational centre of excellence on vetronics to support NATO GVA 7

Creation of a multinational centre of excellence on vetronic...

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7th international conference on Military Technologies, ICMT 2019

作者： Turo, Tomas Ota, Daniel Charchalakis, Periklis University of Defence Faculty of Military Technology Department of Combat and Special Vehicles Kounicova 65 Brno662 10 Czech Republic Fraunhofer Institute for Communication Information Processing and Ergonomics FKIE Fraunhoferstraße 20 Wachtberg53343 Germany Vetronics research Centre VRC Building Lewes Road Brighton East SussexBN2 4GJ United Kingdom

ISBN: (纸本)9781728145938

this article describes the main idea for establishing a Multinational Centre of Excellence (MNCE) in the area of Integrated Electronic Systems for Land Platforms to support NATO Generic Vehicle Architecture (NGVA). the first idea of international cooperation was developed by Executive Secretary of MILVA group in 2010 with a focus on the development of a cooperation between the already existing specialized laboratories and centers of vetronics in the UK, GE and FR. Collaboration with specialists from the University of Defense in Brno began in 2013. In 2014, the Czech Laboratory of Vetronics was officially opened. the grand opening ceremony was attended by representatives of the MILVA Group and the Center of Excellence and research laboratories from GE, FR, SE, UK and CZ. the authors of this article are representatives of three laboratories that are focused on vetronics architectures in military vehicles. © 2019 IEEE.

关键词： Research laboratories

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Research and Implementation of High Performance Traffic processing based on Intel DPDK 9

Research and Implementation of High Performance Traffic Proc...

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9th international conference on parallel architectures, algorithms and Programming (PAAP)

作者： Zhu, Wenjun Li, Peng Luo, Baozhou Xu, He Zhang, Yujie Nanjing Univ Posts & Telecommun Sch Comp Sci Nanjing 210003 Jiangsu Peoples R China Nanjing Univ Posts & Telecommun Sch Comp Sci Jiangsu High Technol Res Key Lab Wireless Sensor Nanjing 210003 Jiangsu Peoples R China

ISBN: (纸本)9781538694039

With the rapid development of Internet and the continuous rise of network users, the network traffic in various regions is increasing rapidly. In the face of a large number of high speed and high throughput of the network environment, traditional packet capture methods and processing capabilities cannot reach the corresponding speed, which results in severe packet loss. this paper focuses on a high-performance packet acquisition and distribution method to break through the performance bottleneck of universal servers and network cards. this paper studies a packet capture method based on DPDK platform, and uses the processing of hash value in RSS to improve the efficiency of data packet distribution, which realizes the process from performance acquisition to efficiently multi-core parallel processing. this method can effectively reduce packet loss and improve the data packet processing rate. It can also reduce resource waste and network overhead for traffic capture and distribution. Preliminary experiments show that DPDK-based traffic processing has obvious advantages over PF-RING and Netmap in data processing speed.

关键词： DPDK Traffic processing Distribution Multi-core parallel processing

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Transient feasibility assessment and enhancement of resilience-oriented distribution grid restoration using parallel simulations

Transient feasibility assessment and enhancement of resilien...

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7th international conference on Renewable Power Generation, RPG 2018

作者： Chen, Ying Zhang, Lu Song, Yankan Gao, Haixiang Department of Electrical Engineering Tsinghua University Beijing China

In recent years, major power outages caused by extreme natural disasters have incurred large economic losses in distribution systems. this study proposes a transient simulation and verification method for resilience-enhancement strategies and proposed a graphics processing unit-based parallel simulation method. the proposed method can be used to verify the transient feasibility of the distribution system before a strategy is actually executed. Simulations are performed to verify the proposed method. © 2019 Institution of Engineering and Technology. All rights reserved.

关键词： Outages

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Cholesky and Gram-Schmidt Orthogonalization for Tall-and-Skinny QR Factorizations on Graphics Processors 25th

Cholesky and Gram-Schmidt Orthogonalization for Tall-and-Ski...

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25th international conference on parallel and Distributed Computing (Euro-Par)

作者： Tomas, Andres E. Quintana-Orti, Enrique S. Univ Jaume 1 Dept Engn & Ciencia Comp Castellon de La Plana 12071 Spain Univ Politecn Valencia Dept Sistemes Informat & Comp Valencia 46022 Spain Univ Politecn Valencia Dept Informat Sistemes & Comp Valencia 46022 Spain

ISBN: (纸本)9783030294007;9783030293994

We present a method for the QR factorization of large tall-and-skinny matrices that combines block Gram-Schmidt and the Cholesky decomposition to factorize the input matrix column panels, overcoming the sequential nature of this operation. this method uses re-orthogonalization to obtain a satisfactory level of orthogonality both in the Gram-Schmidt process and the Cholesky QR. Our approach has the additional benefit of enabling the introduction of a static look-ahead technique for computing the Cholesky decomposition on the CPU while the remaining operations (all Level-3 BLAS) are performed on the GPU. In contrast with other specific factorizations for tall-skinny matrices, the novel method has the key advantage of not requiring any custom GPU kernels. this simplifies the implementation and favours portability to future GPU architectures. Our experiments show that, for tall-skinny matrices, the new approach outperforms the code in MAGMA by a large margin, while it is very competitive for square matrices when the memory transfers and CPU computations are the bottleneck of Householder QR.

关键词： QR factorization Tall-and-skinny matrices Graphics processing unit Gram-Schmidt Cholesky factorization Look-ahead High-performance

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eMDPM: Efficient Multidimensional Pattern Matching Algorithm for GPU 2nd

eMDPM: Efficient Multidimensional Pattern Matching Algorithm...

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2nd international conference on Smart Innovations in Communications and Computational Sciences ICSICCS-2018

作者： Raj, Supragya Chodnekar, Siddha Prabhu Harish, T. Sriraman, Harini School of Computing Science and Engineering Vellore Institute of Technology Chennai Campus Chennai600127 India

ISBN: (纸本)9789811324130

parallelizing pattern matching in multidimensional images is very vital in many applications to improve the performance. With SIMT architectures, the performance can be greatly enhanced if the hardware threads are utilized to the maximum. In the case of pattern matching algorithms, the main bottleneck arises due to the reduction operation that needs to be performed on the multiple parallel search operations. this can be solved by using Shift-Or operations. the recent trend has shown the improvement in pattern matching using Shift-Or operations for bit pattern matching. this has to be extended for multiple dimensional images like hyper-cubes. In this paper, we have extended the Shift-Or pattern matching for multidimensional images. the algorithm is implemented for GPU architectures. the complexity of the proposed algorithm is $$ m*\frac{log(n)}{kw} $$ where m is the number of dimensions, n is the size of the array if the multidimensional matrix values are placed in a single dimensional array, k is the size of the pattern and w is the size of the tile. From the result analysis it is found that the performance is maximum, when the pattern size matches the tile size and it is less than 64. this restriction is due to the size of the warp considered. © 2019, Springer Nature Singapore Pte Ltd.

关键词： Graphics processing unit

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Dynamic Look-up Table Method for Optimizing the Training of Deep Neural Networks on Many-Core Architecture 7

Dynamic Look-up Table Method for Optimizing the Training of ...

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7th IEEE international conference on Computer Science and Network Technology (ICCSNT)

作者： Xia, Jing Ma, Zhong Dai, Xinfa Huang, Weihua He, Li He, Pengyuan Wuhan Digital Engn Inst Wuhan Peoples R China

ISBN: (纸本)9781728132990

Due to the excessive training parameters and computation of Deep Neural Network (DNN) models, we have witnessed the training time increases with the continued increase of the scale of DNN models. Convolution computation is the key step of feature extraction in DNN models and occupies about 90% of the computation operations in DNN models. It is therefore of great necessity to accelerate the speed of convolution calculation in order to improve the training efficiency of system. Currently, the traditional method is to transform convolution computation into matrix multiplication and execute on many-core architecture such as Graphic processing Unit (GPU). However, due to matrix conversion and high computational complexity of matrix multiplication, these methods based on matrix multiplication such as Caffe, consume a lot of time in accessing memory and need to copy redundant data in process of matrix conversion. the low capacity of GPU memory further leads to the low training efficiency of DNN models. therefore, we orchestrate a dynamic look-up table method instead of matrix multiplication to realize convolution calculation in order to optimize the training of DNN on many-core architecture. We further improve the parallelism of the look-up table method in a more fine-grained parallelism by paralleling the building convolution table and look-up table operation based on GPU. In our experiment, we tested and trained MINIST, CIFAR-10, CIFAR-100 and ImageNet data sets respectively. Experiments show that, compared to the original Caffe, the proposed dynamic look-up table method referred as LTP-Caffe can achieve up to 31% speed-up ratio in the training process of DNN models. Experiments further show that LTP-Caffe and Caffe are comparable in accuracy, but the iteration speed of LTP-Caffe is more quickly than the Caffe.

关键词： CNN DNN GPU look-up table parallel

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Transformer design software with parallel processing 19

Transformer design software with parallel processing

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7th international conference on Applied Computing and Information Technology, ACIT 2019

作者： Park, Junhyun Park, Keun-Ho Lee, Hak-Ju Shin, Bum-In Kim, Tae-Ho Park, Kyung-Ho Jang, Ayoung Hahn, Sung-Chin Jo, Jangwu Dept. of Computer Engineering Dong-A University Busan Korea Republic of Dept. of Electrical Engineering Dong-A University Busan Korea Republic of Sanil Seoul Korea Republic of POWERMAX Seoul Korea Republic of KOEMA Seoul Korea Republic of

ISBN: (纸本)9781450371735

the ways of present transformer design can be divided into two types: using spreadsheet like Excel and using design software. Our Zirst work is to develop the design software that can be used by small companies for free. We developed design software which generates as many designs as possible, without aid of expert's knowledge. Our second work is to improve efZiciency by parallelizing the repetitive calculations. the performance of our design software is evaluated by comparing the results obtained from different numbers of cores. We show improvement of execution time where execution of 4 cores is about 45% faster than that of 1 core. © 2019 Association for Computing Machinery. All rights reserved.

关键词： Software design

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Optimizing Machine Learning algorithms on Multi-core and Many-core architectures using thread and Data Mapping 26

Optimizing Machine Learning Algorithms on Multi-core and Man...

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26th Euromicro international conference on parallel, Distributed, and Network-Based processing (PDP)

作者： Serpa, Matheus S. Krause, Arthur M. Cruz, Eduardo H. M. Navaux, Philippe O. A. Pasin, Marcelo Felber, Pascal Fed Univ Rio Grande Sul UFRGS Inst Informat Porto Alegre RS Brazil Univ Neuchatel Neuchatel Switzerland

ISBN: (纸本)9781538649756

Driven by the development of new technologies such as personal assistants or autonomous cars, machine learning has rapidly become one of the most active fields in computer science. the algorithms at the core of machine learning are notoriously demanding in terms of resources. It is therefore of paramount importance to optimize their operation on modern processors. Several approaches have been proposed to accelerate machine learning on GPUs and massively parallel computers, as well as dedicated ASICs. In this paper, we focus on Intel's multi-core Xeon and many-core accelerator Xeon Phi Knights Landing, which can host several hundreds of threads on the same CPU. In such architectures, thread and data mapping are keys for performance. We study the impact of mapping strategies, revealing that, with smart mapping policies, one can indeed significantly speed up machine learning applications on manycore architectures. Execution time was reduced by up to 25.2% and 18.5% on Intel Xeon and Xeon Phi KNL, respectively.

关键词： Machine learning thread mapping Data mapping Memory accesses

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PRINS: processing-in-Storage Acceleration of Machine Learning

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2018年第5期17卷 889-896页

作者： Kaplan, Roman Yavits, Leonid Ginosar, Ran Technion Israel Inst Technol Dept Elect Engn IL-3547902 Haifa Israel

Machine learning algorithms have become a major tool in various applications. the high-performance requirements on large-scale datasets pose a challenge for traditional von Neumann architectures. We present two machine learning implementations and evaluations on PRINS, a novel processing-in-storage system based on resistive content addressable memory (ReCAM). PRINS functions simultaneously as a storage and a massively parallel associative processor. PRINS processing-in-storage resolves the bandwidth wall faced by near-data von Neumann architectures, such as three-dimensional DRAM and CPU stack or SSD with embedded CPU, by keeping the computing inside the storage arrays, thus implementing in-data, rather than near-data, processing. We show that PRINS-based processing-in-storage architecture may outperform existing in-storage designs and acceleratorbased designs. Multiple performance comparisons for the ReCAM processing-in-storage implementations ofK-means and K-nearest neighbors are performed. Compared platforms include CPU, GPU, FPGA, and Automata Processor. We show that PRINSmay achieve an order-of-magnitude speedup and improved power efficiency relative to all compared platforms.

关键词： Near-data processing associative processing processing-in-storage processing-in-memory RRAM CAM memristors

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