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Hybrid elastic arm & cloud hpc collaborative platform for generic tasks 7th

Hybrid elastic arm & cloud hpc collaborative platform for ge...

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7th international conference on Cloud Computing and Big Data, JCC and BD 2019

作者： Petrocelli, David Giusti, Armando De Naiouf, Marcelo Computer Science School La Plata National University 50 and 120 La Plata Argentina Lujan National University 5 and 7 Routes Luján Argentina Computer Science School La Plata National University-CIC-PBA 50 and 120 Buenos Aires Argentina CONICET-National Council of Scientific and Technical Research Buenos Aires Argentina

ISBN: (纸本)9783030277123

Compute-heavy workloads are currently run on Hybrid HPC structures using x86 CPUs and GPUs from Intel, AMD, or NVidia, which have extremely high energy and financial costs. However, thanks to the incredible progress made on CPUs and GPUs based on the ARM architecture and their ubiquity in today’s mobile devices, it’s possible to conceive of a low-cost solution for our world’s data processing needs. Every year ARM-based mobile devices become more powerful, efficient, and come in ever smaller packages with ever growing storage. At the same time, smartphones waste these capabilities at night while they’re charging. this represents billions of idle devices whose processing power is not being utilized. For that reason, the objective of this paper is to evaluate and develop a hybrid, distributed, scalable, and redundant platform that allows for the utilization of these idle devices through a cloud-based administration service. the system would allow for massive improvements in terms of efficiency and cost for compute-heavy workload. During the evaluation phase, we were able to establish savings in power and cost significant enough to justify exploring it as a serious alternative to traditional computing architectures. © Springer Nature Switzerland AG 2019.

关键词： Smartphones

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A Malleable Vectorized Auction Algorithm for Modern Multicore architectures 20

A Malleable Vectorized Auction Algorithm for Modern Multicor...

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20th IEEE international conference on High Performance Computing and Communications (HPCC) / 16th IEEE international conference on Smart City (SmartCity) / 4th IEEE international conference on Data Science and Systems (DSS)

作者： Sena, A. C. Marzulo, L. A. J. Nascimento, A. P. Vasconcelos, C. N. Univ Estado Rio De Janeiro Inst Matemat & Estat Rio De Janeiro Brazil Univ Fed Fluminense Inst Comp Niteroi RJ Brazil

ISBN: (纸本)9781538666142

the auction algorithm has been widely used to solve the bipartite graph matching problem and its parallel implementation is employed to find solutions in a reasonable computational time. Moreover, the new multicore architectures, besides its various cores, have a SIMD instruction set that can increase application performance when exactly the same operations are to be performed on multiple data objects. the aim of this paper is to efficiently execute the auction algorithm on these architectures. To achieve that, a vectorized version was implemented and evaluated. these versions were then run in parallel using the OpenMP library. Finally, to optimize the number of threads used during the execution, a malleable strategy is proposed and evaluated. Results show that the vectorized version outperforms the sequential one by a factor of 10, while the malleable vectorized version was able to adapt its execution to exploit the full potential of multicore architectures.

关键词： Multicore processing Heuristic algorithms Program processors Indexes Bipartite graph conferences

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Automated Ocular Artifacts Identification and Removal from EEG Data Using Hybrid Machine Learning Methods

Automated Ocular Artifacts Identification and Removal from E...

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international conference on Signal processing and Integrated Networks (SPIN)

作者： Mohit Sarin Akshat Verma Deepthi Hitesh Mehta Praveen Kumar Shukla Shrish Verma Department of Electronics and Communication Engineering National Institute of Technology Raipur India

ISBN: (数字)9781728154756

ISBN: (纸本)9781728154763

Brain Computer Interface (BCI) is an emerging field of research, which helps neuromuscular disabled people to communicate and control external devices with the brain. Electroencephalogram (EEG) signals have been used by doctors to diagnose brain activities. EEG signals are very sensitive to the physical movement of most of the body parts. Electrooculogram (EOG) are the signals which are directly related to eye movements. In the field of BCI, artifacts refer to those signals which are not required but will be present in data because of the involuntary actions of human muscles. In the proposed research, BCI Competition III Dataset IV A is used, which consists of two classes of signals right hand and right foot, so ocular artifacts were a prime hindrance for this type of data. the research involves the use of the following feature detection methods: ICA, ICA-RLS, ICA-LMS, ICA-DWT, EMD-ICA. the first common step is using ICA to obtain independent components(ICs). Using ICA, ICs that contain ocular artifacts can be identified and then further exposed to another round of ICA or adaptive filtering that uses LMS, RLS. the adaptive filtering technique reduces the need for parallel EOG recordings by removing the ocular ICs using reference signals. Hybrid' methods have gained much advantage over the traditional ICA process, which leads to better detection and removal of ocular artifacts with these techniques. Further, the research proposes a system involving the use of SVM-PSO for the classification of motor imagery signals obtained after the removal of artifacts. ICA-RLS and CSP as pre-processing and feature extraction techniques provided the best classification accuracy of 92.94%.

关键词： Signal processing conferences Noise reduction Tools Manganese

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Accelerating FM-index Search for Genomic Data processing 18

Accelerating FM-index Search for Genomic Data Processing

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47th international conference on parallel processing (ICPP)

作者： Wang, Yuanrong Li, Xueqi Zang, Dawei Tan, Guangming Sun, Ninghui Univ Chinese Acad Sci CAS ICT SKL Comp Architecture Beijing Peoples R China Chinese Acad Sci SKL Comp Architecture ICT Beijing Peoples R China

ISBN: (纸本)9781450365109

the deluge of genomics data is incurring prohibitively high computational costs. As an important building block for genomic data processing algorithms, FM-index search occupies most of execution time in sequence alignment. Due to massive random streaming memory references relative to only small amount of computations, FM-index search algorithm exhibits extremely low efficiency on conventional architectures. this paper proposes Niubility, an accelerator for FM-index search in genomic sequence alignment. Based on our algorithm-architecture co-design analysis, we found that conventional architectures exploit low memory-level parallelism so that the available memory bandwidth cannot be fully utilized. Niubility accelerator customizes bit-wise operations and exploit data-level parallelism, that produces maximal concurrent memory accesses to saturate memory bandwidth. We implement an accelerator ASIC in a ST 28nm process that achieves up to 990x speedup over the state-of-the-art software.

关键词： Energy efficiency Hardware-acceleration Genome alignment

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A Spark-based parallel framework for geospatial raster data processing 7

A Spark-based parallel framework for geospatial raster data ...

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7th international conference on Agro-Geoinformatics (Agro-Geoinformatics)

作者： Gao, Fan Yue, Peng Wuhan Univ Sch Remote Sensing & Informat Engn 129 Luoyu Rd Wuhan 430079 Hubei Peoples R China

ISBN: (纸本)9781538650394

With the rapid development of geospatial sensor technologies in recent years, the acquisition of higher resolution of spatial and temporal data is becoming common, resulting in an explosive increase in the volume of geospatial data. Meanwhile, the sophistication and complexity of geospatial algorithms is also increasing. the current geospatial applications often have limited capabilities in dealing with the trend. In this paper, we proposed a Spark-based parallel framework for geospatial raster data processing. the framework provides a parallel processing way for both a single high-resolution remote sensing image with large size using a RsImage model and multiple remote sensing images with small size using a RsBundleImage model. Taking the edge extraction from remote sensing images as an example, the paper demonstrates how the framework can improve the efficiency of the Canny edge detector by achieving the ratio of speedup up to 7.0 similar to 8.0.

关键词： Spark RsImage model RsBundleImage model

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An Efficient Graph Accelerator with parallel Data Conflict Management 18

An Efficient Graph Accelerator with Parallel Data Conflict M...

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27th IEEE/ACM/IFIP international conference on parallel architectures and Compilation Techniques (PACT)

作者： Yao, Pengcheng Zheng, Long Liao, Xiaofei Jin, Hai He, Bingsheng Huazhong Univ Sci & Technol Big Data Technol & Syst Lab Cluster & Grid Comp Lab Serv Comp Technol & Syst Lab Wuhan 430074 Hubei Peoples R China Natl Univ Singapore Sch Comp Singapore 117418 Singapore

ISBN: (纸本)9781450359863

Graph-specific computing with the support of dedicated accelerator has greatly boosted the graph processing in both efficiency and energy. Nevertheless, their data conflict management is still sequential when certain vertex needs a large number of conflicting updates at the same time, leading to prohibitive performance degradation. this is particularly true and serious for processing natural graphs. In this paper, we have the insight that the atomic operations for the vertex updating of many graph algorithms (e.g., BFS, PageRank, and WCC) are typically incremental and simplex. this hence allows us to parallelize the conflicting vertex updates in an accumulative manner. We architect AccuGraph, a novel graph-specific accelerator that can simultaneously process atomic vertex updates for massive parallelism while ensuring the correctness. A parallel accumulator is designed to remove the serialization in atomic protections for conflicting vertex updates through merging their results in parallel. Our implementation on Xilinx FPGA with a wide variety of typical graph algorithms shows that our accelerator achieves an average throughput by 2.36 GTEPS as well as up to 3.14x performance speedup in comparison with state-of-the-art ForeGraph (with its single-chip version).

关键词： Atoms

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A Customized processing-in-Memory Architecture for Biological Sequence Alignment 29

A Customized Processing-in-Memory Architecture for Biologica...

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29th Annual IEEE international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Akbari, Nasrin Modarressi, Mehdi Daneshtalab, Masoud Loni, Mohammad Univ Tehran Coll Engn Dept Elect & Comp Engn Tehran Iran Inst Res Fundamental Sci IPM Sch Comp Sci Tehran Iran Malardalen Univ MDH Vasteras Sweden Royal Inst Technol KTH Stockholm Sweden

ISBN: (纸本)9781538674796

Sequence alignment is the most widely used operation in bioinformatics. With the exponential growth of the biological sequence databases, searching a database to find the optimal alignment for a query sequence (that can be at the order of hundreds of millions of characters long) would require excessive processing power and memory bandwidth. Sequence alignment algorithms can potentially benefit from the processing power of massive parallel processors due their simple arithmetic operations, coupled with the inherent fine-grained and coarse-grained parallelism that they exhibit. However, the limited memory bandwidth in conventional computing systems prevents exploiting the maximum achievable speedup. In this paper, we propose a processing-in-memory architecture as a viable solution for the excessive memory bandwidth demand of bioinformatics applications. the design is composed of a set of simple and lightweight processing elements, customized to the sequence alignment algorithm, integrated at the logic layer of an emerging 3D DRAM architecture. Experimental results show that the proposed architecture results in up to 2.4x speedup and 41% reduction in power consumption, compared to a processor-side parallel implementation.

关键词： Sequence Alignment Accelerator processing-in-memory

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Massively parallel Skyline Computation For processing-In-Memory architectures 18

Massively Parallel Skyline Computation For Processing-In-Mem...

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27th IEEE/ACM/IFIP international conference on parallel architectures and Compilation Techniques (PACT)

作者： Zois, Vasileios Gupta, Divya Tsotras, Vassilis J. Najjar, Walid A. Roy, Jean-Francois Univ Calif Riverside Riverside CA 92521 USA UPMEM SAS Grenoble France

ISBN: (纸本)9781450359863

processing-In-Memory (PIM) is an increasingly popular architecture aimed at addressing the 'memory wall' crisis by prioritizing the integration of processors within DRAM. It promotes low data access latency, high bandwidth, massive parallelism, and low power consumption. the skyline operator is a known primitive used to identify those multi-dimensional points offering optimal trade-offs within a given dataset. For large multidimensional dataset, calculating the skyline is extensively compute and data intensive. Although, PIM systems present opportunities to mitigate this cost, their execution model relies on all processors operating in isolation with minimal data exchange. this prohibits direct application of known skyline optimizations which are inherently sequential, creating dependencies and large intermediate results that limit the maximum parallelism, throughput, and require an expensive merging phase. In this work, we address these challenges by introducing the first skyline algorithm for PIM architectures, called DSky. It is designed to be massively parallel and throughput efficient by leveraging a novel work assignment strategy that emphasizes load balancing. Our experiments demonstrate that it outperforms the state-of-the-art algorithms for CPUs and GPUs, in most cases. DSky achieves 2x to 14x higher throughput compared to the state-of-the-art solutions on competing CPU and GPU architectures. Furthermore, we showcase DSky's good scaling properties which are intertwined with PIM's ability to allocate resources with minimal added cost. In addition, we showcase an order of magnitude better energy consumption compared to CPUs and GPUs.

关键词： processing-in-memory skyline queries pareto dominance massive parallelism processing-near-memory load balancing

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Vectorized parallel Sparse Matrix-Vector Multiplication in PETSc Using AVX-512 18

Vectorized Parallel Sparse Matrix-Vector Multiplication in P...

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47th international conference on parallel processing (ICPP)

作者： Zhang, Hong Mills, Richard T. Rupp, Karl Smith, Barry F. Argonne Natl Lab Math & Comp Sci Div Lemont IL 60439 USA TU Wien Inst Microelect Vienna Austria

ISBN: (纸本)9781450365109

Emerging many-core CPU architectures with high degrees of single-instruction, multiple data (SIMD) parallelism promise to enable increasingly ambitious simulations based on partial differential equations (PDEs) via extreme-scale computing. However, such architectures present several challenges to their efficient use. Here, we explore the efficient implementation of sparse matrix-vector (SpMV) multiplications-a critical kernel for the workhorse iterative linear solvers used in most PDE-based simulations-on recent CPU architectures from Intel as well as the second-generation Knights Landing Intel Xeon Phi, which features many CPU cores, wide SIMD lanes, and on-package high-bandwidth memory. Traditional SpMV algorithms use compressed sparse row storage format, which is a hindrance to exploiting wide SIMD lanes. We study alternative matrix formats and present an efficient optimized SpMV kernel, based on a sliced ELLPACK representation, which we have implemented in the PETSc library. In addition, we demonstrate the benefit of using this representation to accelerate preconditioned iterative solvers in realistic PDE-based simulations in parallel.

关键词： parallel SpMV PETSc vectorization many-core Xeon Phi

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Expediting parallel Graph Connectivity algorithms 25

Expediting Parallel Graph Connectivity Algorithms

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25th IEEE international conference on High Performance Computing, Data and Analytics (HiPC)

作者： Wadwekar, Mihir Kothapalli, Kishore Int Inst Informat Technol Hyderabad 500032 India

ISBN: (纸本)9781538683866

Finding whether a graph is k-connected, and the identification of its k-connected components is a fundamental problem in graph theory. For this reason, there have been several algorithms for this problem in both the sequential and parallel settings. Several recent sequential and parallel algorithms for k-connectivity rely on one or more breadth-first traversals of the input graph. While BFS can be made very efficient in a sequential setting, the same cannot be said in the case of parallel environments. A major factor in this difficulty is due to the inherent requirement to use a shared queue, balance work among multiple threads in every round, synchronization, and the like. Optimizing the execution of BFS on many current parallel architectures is therefore quite challenging. For this reason, it can be noticed that the time spent by the current parallel graph connectivity algorithms on BFS operations is usually a significant portion of their overall runtime. In this paper, we study how one can, in the context of algorithms for graph connectivity, mitigate the practical inefficiency of relying on BFS operations in parallel. Our technique suggests that such algorithms may not require a BFS of the input graph but actually can work with a sparse spanning subgraph of the input graph. the incorrectness introduced by not using a BFS spanning tree can then be offset by further post-processing steps on suitably defined small auxiliary graphs. Our experiments on finding the 2, and 3-connectivity of graphs on Nvidia K40c GPUs improve the state-of-the-art on the corresponding problems by a factor 2.2x, and 2.1x respectively.

关键词： Testing parallel algorithms Phase change random access memory Graphics processing units Data structures Synchronization

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