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An Efficient Network IDS for Cloud Environments Based on a Combination of Deep Learning and an Optimized Self-adaptive Heuristic Search Algorithm 7th

An Efficient Network IDS for Cloud Environments Based on a C...

引用

7th international conference on Networked Systems (NETYS)

作者： Chiba, Zouhair Abghour, Noreddine Moussaid, Khalid El Omri, Amina Rida, Mohamed Hassan II Univ Casablanca Fac Sci Ain Chock LIMSAD Labs Casablanca 20100 Morocco

ISBN: (纸本)9783030312770;9783030312763

Nowadays, Cloud Computing (CC) is one of the fastest emerging core technologies in the current information era. It is leading a new revolution on the ways of data storage and calculation. CC remains gaining traction among organizations thanks to its appealing features like pay-per-use model for billing customers, elasticity, ubiquity, scalability and availability of resources for businesses. Hence, many organizations are moving their workloads or processes to cloud due to its inherent advantages. Nevertheless, several security issues arise with the transition to this computing paradigm including intrusion detection. Attackers and intruders developed new sophisticated tools defeating traditional Intrusion Detection Systems (IDS) by huge amount of network traffic data and dynamic behaviors. the existing Cloud IDSs suffer from low detection accuracy and high false positive rate. To overcome this issue, we propose a smart approach using a self-adaptive heuristic search algorithm called "Improved Self-Adaptive Genetic Algorithm" (ISAGA) to build automatically a Deep Neural Network (DNN) based Anomaly Network Intrusion Detection System (ANIDS). ISAGA is a variant of standard Genetic Algorithm (GA), which is developed based on GA improved through an Adaptive Mutation Algorithm (AMA) and optimization strategies. the optimization strategies carried out are parallel processing and Fitness Value Hashing that reduce execution time, convergence time and save processing power. Our approach consists of using ISAGA with the goal of searching the optimal or near optimal combination of most relevant values of the parameters included in construction of DNN based IDS or impacting its performance, like feature selection, data normalization, architecture of DNN, activation function, learning rate and Momentum term, which ensure high detection rate, high accuracy and low false alarm rate. CloudSim 4.0 simulator platform and CICIDS2017 dataset were used for simulation and validation of the

关键词： Cloud computing Anomaly detection Network intrusion detection system Deep Neural Network Optimization Genetic algorithm Adaptive Mutation Algorithm Heuristic search algorithm parallel processing Fitness value hashing CICIDS2017 dataset

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GAP-8: A RISC-V SoC for AI at the Edge of the IoT 29

GAP-8: A RISC-V SoC for AI at the Edge of the IoT

引用

29th Annual IEEE international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Flamand, Eric Rossi, Davide Conti, Francesco Loi, Igor Pullini, Antonio Rotenberg, Florent benini, Luca GreenWaves Technol Villard Bonnot France Univ Bologna DEI Bologna Italy Swiss Fed Inst Technol Integrated Syst Lab Zurich Switzerland

ISBN: (纸本)9781538674796

Current ultra-low power smart sensing edge devices, operating for years on small batteries, are limited to low-bandwidth sensors, such as temperature or pressure. Enabling the next generation of edge devices to process data from richer sensors such as image, video, audio, or multi-axial motion/vibration has huge application potential. However, edge processing of data-rich sensors poses the extreme challenge of squeezing the computational requirements of advanced, machine-learning-based near-sensor data analysis algorithms (such as Convolutional Neural Networks) within the mW-range power envelope of always-ON battery-powered IoT end-nodes. To address this challenge, we propose GAP-8: a multi-GOPS fully programmable RISC-V IoT-edge computing engine, featuring a 8-core cluster with CNN accelerator, coupled with an ultra-low power MCU with 30 mu W state-retentive sleep power. GAP-8 delivers up to 10 GMAC/s for CNN inference (90 MHz, 1.0V) at the energy efficiency of 600 GMAC/s/W within a worst-case power envelope of 75 mW.

关键词： Edge processing Internet of things Convolutional Neural Networks Near Sensor processing parallel architectures

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A comparison of practical and computational approaches to design modular product architecture for products with medium complexity: A case study on computer numerical control machine 1

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7th international conference on Research into Design, ICoRD 2019

作者： Choudhuri, Ayushman Upadhyay, Pankaj Yevalkar, Abhishek Manipal Institute of Technology ManipalKarnataka India Indian Institute of Technology Guwahati GuwahatiAssam India

ISBN: (数字)9789811359743

ISBN: (纸本)9789811359736

A typical methodology for product architecture design of complex products using Design Structure Matrix (DSM) uses a "bottom-up" approach where an algorithm suggests the ideal cluster of components. In the current research, we use a manual "top-down" approach to generate a modular product architecture for medium complexity product. We used a typical computational tool called IGTA for the "bottom-up" approach but found that the algorithm does not produce results which are practically applicable. A manual approach based on critical observation of the functional diagram of the product, product interactions, and verification of the modules using a Design Structure Matrix is more suitable. the paper compares the results of both approaches for the same product architecture considering a case study of a moving gantry based double-actuated Computer Numerical Control (CNC) milling machine. It is reported that manual "top-down" approaches are more suitable for medium complexity products than algorithmic bottom-up approaches. © 2019, Springer Nature Singapore Pte Ltd.

关键词： parallel processing systems

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Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study 29

Invasive Computing for Predictability of Multiple Non-functi...

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29th Annual IEEE international conference on Application-Specific Systems, architectures and Processors (ASAP)

作者： Sousa, Ericles Witterauf, Michael Brand, Marcel Tanase, Alexandru Hannig, Frank Teich, Juergen Friedrich Alexander Univ Erlangen Numberg FAU Erlangen Germany

ISBN: (纸本)9781538674796

the predictability of non-functional execution qualities is of utmost importance for the successful introduction of multi-core architectures in embedded systems requiring guarantees rather than best effort behavior. Due to the exclusive utilization of claimed resources, invasive computing provides isolation of applications on multi-core systems. this provides composability that allows to characterize and analyze individual applications statically and independent from others. In this paper, we demonstrate the principles of this resource-aware computing paradigm as an enabler for predictability of multiple non-functional properties, i.e., timing and reliability, applied to a cyber-physical system. In particular, we present the application and multi-processor implementation of a reliable and time-predictable acceleration of object detection algorithms for hard real-time control of an inverted pendulum.

关键词： Reliability Runtime Program processors Timing Uncertainty Computer architecture parallel processing"

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POWER: A parallel-Optimization-Based Framework Towards Edge Intelligent Image Recognition and a Case Study 18th

POWER: A Parallel-Optimization-Based Framework Towards Edge ...

引用

18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Yang, Yingyi Mai, Xiaoming Wu, Hao Nie, Ming Wu, Hui Guangdong Power Grid Co Ltd Elect Power Res Inst Guangzhou Peoples R China

ISBN: (纸本)9783030050511;9783030050504

To improve the intelligent image recognition abilities of edge devices, a parallel-optimization-based framework called POWER is introduced in this paper. With FPGA (Field-Programmable Gate Array) as its hardware module, POWER provides well extensibility and flexible customization capability for developing intelligent firmware suitable for different types of edge devices in various scenarios. through an actual case study, we design and implement a firmware prototype following the specification of POWER and explore its performance improvement using parallel optimization. Our experimental results show that the firmware prototype we implement exhibits good performance and is applicable to substation inspection robots, which also validate the effectiveness of our POWER framework in designing edge intelligent firmware modules indirectly.

关键词： Edge intelligence Image recognition Framework parallel optimization Substation inspection robot

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Asynchronous parallel Dijkstra's Algorithm on Intel Xeon Phi Processor How to Accelerate Irregular Memory Access Algorithm 18th

Asynchronous Parallel Dijkstra's Algorithm on Intel Xeon Phi...

引用

18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Zhang, Weidong Zhang, Lei Chen, Yifeng Peking Univ EECS Beijing 100871 Peoples R China HuaWei Inc Shenzhen Peoples R China

ISBN: (纸本)9783030050511;9783030050504

As the instruction-level parallelism (ILP) on CPU develops to a rather advanced level, the exploration that whether many-core architecture is applicable for graph algorithms is generating more interests in researchers. However, due to the irregular memory access and the low ratio of computation to memory access, the performance of graph algorithms on many-core architectures has never worked good enough. To obtain outstanding speedup on many-core architecture, first of all, we need to figure out three questions: (i) how to optimize the memory access, (ii) how to minimize the overhead of synchronization, (iii) how to exploit the parallelism in algorithm. Prior works hardly reach the goal if such questions are treated in separated way. throughout this paper, we aim to settle these questions systematically, and try to provide a set of methods of optimizing graph algorithms on many-core architecture. this paper mainly discusses how to accelerate the Single Source Shortest Path (SSSP) problem on Intel Many Integrated Core (MIC) architecture, on which we propose an asynchronous parallel Dijkstra's algorithm. It aims at maximizing parallelism and minimizing overhead of synchronization. Experimental result shows that the MIC architecture could efficiently solve the SSSP problem, and its performance could be sped up by 9.2x compared to the benchmark of DIMACS.

关键词： Single source shortest path parallel algorithm Intel MIC Road network

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A Caching-Based parallel FP-Growth in Apache Spark 1

引用

18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Cai, Zhicheng Zhu, Xingyu Zheng, Yuehui Liu, Duan Xu, Lei Nanjing Univ Sci & Technol Sch Comp Sci & Engn Nanjing Peoples R China

ISBN: (数字)9783030050573

ISBN: (纸本)9783030050573;9783030050566

the association-rule-based recommendation is widespread in many big data applications which need quick response to improve user experience. Spark is a widely used distributed computing platform, which accelerates the processing of large-scale distributed data. Developing appropriate distributed algorithm for Spark is essential to decrease the processing time of distributed recommendation. the existing FP-Growth in Spark is a popular parallel recommendation method but getting the best performance only when the memory of machines can accommodate all immediate Resilient Distributed DataSets (RDDs). However, memory of many practice data centers is still not large enough for large data sets. therefore, in this paper, a caching-based parallel FP-Growth is proposed which consists of an integer-based sorting and an RDD-caching strategy to improve the efficiency. Experimental results show that the proposal decreases the execution time by 32.37% on average compared with the existing parallel FP-Growth in Spark. Furthermore, impacts of some important parameters upon the performance of the proposal are analyzed by numerous realistic experiments in Spark.

关键词： Spark parallel FP-Growth Caching strategy

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vPlacer: A Co-scheduler for Optimizing the Performance of parallel Jobs in Xen 18th

vPlacer: A Co-scheduler for Optimizing the Performance of Pa...

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18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Jiang, Peng He, Ligang Ren, Shenyuan Chen, Zhiyan Mao, Rui Univ Warwick Dept Comp Sci Coventry CV4 7ES W Midlands England Shenzhen Univ Coll Comp Sci & Software Engn Shenzhen Peoples R China

ISBN: (纸本)9783030050511;9783030050504

Xen, a popular virtualization platform which enables multiple operating systems sharing one physical host, has been widely used in various fields nowadays. Currently, the existing schedulers of Xen are initially targeting at serial jobs, which achieves a remarkable utilization of computer hardware and impressive overall performance. However, the virtualized systems are expected to accommodate both parallel jobs and serial jobs in practice, and resource contention between virtual machines results in severe performance degradation of the parallel jobs. Moreover, the physical resource is vastly wasted during the communication process due to the ineffective scheduling of parallel jobs. this paper aims to optimize the performance of the parallel jobs in Xen using the co-scheduling mechanism. In this paper, we statistically analyze the process of scheduling parallel jobs in Xen, which points out that the credit scheduler is not capable of properly scheduling a parallel job. Moreover, we propose vPlacer, a conservative co-scheduler to improve the performance of the parallel job in Xen. Our co-scheduler is able to identify the parallel jobs and optimize the scheduling process to satisfy the particularity of the parallel job. the prototype of our vPlacer is implemented, and the experimental results show that the performance of the parallel job is significantly improved and the utilization of the hardware resource is optimized.

关键词： Xen Virtualization parallel job Scheduler

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A parallel Method for All-Pair SimRank Similarity Computation 18th

A Parallel Method for All-Pair SimRank Similarity Computatio...

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18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Huang, Xuan Gao, Xingkun Tang, Jie Wu, Gangshan Nanjing Univ Dept Comp Sci & Technol Nanjing 210023 Peoples R China Nanjing Univ State Key Lab Novel Software Technol Nanjing 210023 Peoples R China

ISBN: (纸本)9783030050511;9783030050504

How to measure SimRank similarity of all-pair vertices in a graph is a very important research topic which has a wide range of applications in many fields. However, computation of SimRank is costly in both time and space, making traditional computing methods failing to handle graph data of ever-growing size. this paper proposes a parallel multi-level solution for all-pair SimRank similarity computing on large graphs. We partition the objective graph first with the idea of modularity maximization and get a collapsed graph based on the blocks. then we compute the similarities between verteices inside a block as well as the similarities between the blocks. In the end, we integrate these two types of similarities and calculate the approximate SimRank simlarities between all vertex pairs. the method is implemented on Spark platform and it makes an improvement on time efficiency while maintaining the effectiveness compared to SimRank.

关键词： SimRank similarity Spark parallel computing

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parallel Communication Mechanisms in Solving Integral Equations for Electromagnetic Scattering Based on the Method of Moments 18th

Parallel Communication Mechanisms in Solving Integral Equati...

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18th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Song, Lan Peters, Dennis K. Huang, Weimin Liu, Zhiwei Lei, Lixia Wen, Tangliu Wuhan Univ Sch Comp State Key Lab Software Engn Wuhan 430072 Hubei Peoples R China East China Jiaotong Univ Sch Informat Engn Nanchang 330013 Jiangxi Peoples R China Mem Univ Fac Engn & Appl Sci Elect & Comp Engn St John NF Canada

ISBN: (纸本)9783030050511;9783030050504

In this paper, a parallel solution of impedance filling was studied to improve the efficiency for the method of moments (MOM) in solving the integral equation for electromagnetic scattering. Based on the formalization method, the correctness verification method of the parallel communication protocol was proposed to avoid the abnormal situation such as deadlock caused by unsynchronized MPI message delivery. Finally, a numerical example is given to verify the accuracy of the parallel algorithm in a multi-core cluster environment, and the parallel efficiency and computational capability are also tested. From the experiment data, it can be seen that the results of the parallel-based integral equation match well with the results of the Mie analytical solution. the parallel algorithm proposed in this paper is evaluated in terms of the acceleration ratio and parallel efficiency. the experimental results demonstrate the reliability and effectiveness of the method.

关键词： Formal verification parallel communication Electromagnetic scattering Petri net

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