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A java code protection scheme via dynamic recovering runtime instructions 18th

A java code protection scheme via dynamic recovering runtime...

引用

18th international conference on algorithms and architectures for parallel processing, ICA3PP 2018

作者： Jiajia, Sun Jinbao, Gao Yu-an, Tan Yu, Zhang Xiao, Yu School of Computer Science and Technology Beijing Institute of Technology Beijing100081 China School of Electrical and Information Engineering Beijing Key Laboratory of Intelligent Processing for Building Big Data Beijing University of Civil Engineering and Architecture Beijing100044 China China University of Mining and Technology Beijing100083 China Department of Computer Science and Technology Shandong University of Technology ZiboShandong255022 China

ISBN: (纸本)9783030050627

As Android operating system and applications on the device play important roles, the security requirements of Android applications increased as well. With the upgrade of Android system, Android runtime mode (ART mode) has gradually become the mainstream architecture of the Android operating system. ART introduces several improvements in Android, but it also introduces new ways to enhance malicious activities. this paper proposed a confidential finer granularity protection scheme for application programs under ART mode of ROOT Android devices. Taking Java method as the protection granularity, the protection scheme increased the accuracy of protecting targets. In addition, the protection scheme provided a more thorough protection for applications by combining dynamic loading technology and encryption technology in ART mode, and improved the security of Android applications. Experiments showed that the proposed protection scheme is effective. © Springer Nature Switzerland AG 2018.

关键词： Android (operating system)

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Cache Friendly Strategies to Optimize Matrix Multiplication 7

Cache Friendly Strategies to Optimize Matrix Multiplication

引用

7th IEEE international Advance Computing conference (IACC)

作者： Ananth, M. Vishwas, S. Anala, M. R. RV Coll Engn Dept Comp Sci & Engn Bangalore Karnataka India

ISBN: (纸本)9781509015603

Matrix multiplication is an operation used in many algorithms with a plethora of applications ranging from Image processing, Signal processing, to Artificial Neural Networks and Linear algebra. this work aims to showcase the effect of developing matrix multiplication strategies that are less time and processor intensive by effectively handling memory accesses. the paper also touches upon on the advantages of using OpenMP, a multiprocessing toolkit to show the effect of parallelizing matrix multiplication

关键词： Matrix multiplication OpenMP cache friendly parallel cache blocking C pointers

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Graphie: Large-Scale Asynchronous Graph Traversals on Just a GPU 26

Graphie: Large-Scale Asynchronous Graph Traversals on Just a...

引用

26th international conference on parallel architectures and Compilation Techniques (PACT)

作者： Han, Wei Mawhirter, Daniel Wu, Bo Buland, Matthew Colorado Sch Mines Dept Comp Sci Golden CO 80401 USA Salesforce Louisville CO USA Colorado Sch Mines Golden CO 80401 USA

ISBN: (纸本)9781509067640

Most GPU-based graph systems cannot handle large-scale graphs that do not fit in the GPU memory. the ever-increasing graph size demands a scale-up graph system, which can run on a single GPU with optimized memory access efficiency and well-controlled data transfer overhead. However, existing systems either incur redundant data transfers or fail to use shared memory. In this paper we present Graphie, a system to efficiently traverse large-scale graphs on a single GPU. Graphie stores the vertex attribute data in the GPU memory and streams edge data asynchronously to the GPU for processing. Graphie's high performance relies on two renaming algorithms. the first algorithm renames the vertices so that the source vertices can be easily loaded to the shared memory to reduce global memory accesses. the second algorithm inserts virtual vertices into the vertex set to rename real vertices, which enables the use of a small boolean array to track active partitions. the boolean array also resides in shared memory and can be updated in constant time. the renaming algorithms do not introduce any extra overhead in the GPU memory or graph storage on disk. Graphie's runtime overlaps data transfer with kernel execution and reuses transferred data in the GPU memory. the evaluation of Graphie on 7 real-world graphs with up to 1.8 billion edges demonstrates substantial speedups over X-Stream, a state-of-the-art edge-centric graph processing framework on the CPU, and GraphReduce, an out-of-memory graph processing systems on GPUs.

关键词： Graph Traversal GPUs Out-Of-Memory processing Data Transformation

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Tree Structured Data processing on GPUs 7

Tree Structured Data Processing on GPUs

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7th international conference on Cloud Computing, Data Science and Engineering (Confluence)

作者： Lu, Yifan Yang, Lu Bhavsar, Virendrakumar C. Kumar, Neetesh Univ New Brunswick Fredericton Dept Comp Sci Fredericton NB E3B 5A3 Canada Delhi Technol Univ Dept Comp Sci & Engn Delhi 110042 India

ISBN: (纸本)9781509035199

In order to reduce the computing time for processing large tree-structured data sets, parallel processing has been used. Recently, research has been done on parallel computing of tree-structured data on Graphics processing Units (GPUs). GPU device cannot directly access the tree structured data on hard disks which is commonly stored as objects or linked-lists. So, it is required to copying this tree structured data from hard disk to device memory for the computation and copying tree structured data in its normal structure is very costly because of lots of pointers overhead. Existing tree data structures on GPUs are commonly applied to storing a particular kind of tree, and support limited types of tree traversals. In this work, a tree data structure is proposed to store different kind of trees as a linear data structure (fast in copying). the proposed data structure is applied on general trees and binary trees and supports four common types of tree traversals: pre-order, post-order, in-order and breadth-first traversals. therefore, most of the tree algorithms can be implemented on GPUs by using this proposed data structure. the results show that the proposed data structure is successfully implemented for all the traversals for binary as well as general trees.

关键词： Tree traversals GPU binary tree general tree CUDA parallel processing

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Scaling Analysis of Solving algorithms for Canonical Problem of Dispatching in the Context of Dynamic Programming 7

Scaling Analysis of Solving Algorithms for Canonical Problem...

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7th international conference Internet Technologies and Applications (ITA)

作者： Fedosenko, Yuriy S. Reznikov, Mikhail B. Plekhov, Aleksandr S. Chakirov, Roustiam Houlden, Nigel Volga State Univ Water Transportat 5 Nesterov St Nizhnii Novgorod 603005 Russia Alekseev Nizhny Novgorod State Tech Univ 24 Minin St Nizhnii Novgorod 603155 Russia Bonn Rhein Sieg Univ Appl Sci 20 Grantham Allee D-53757 St Augustin Germany Glyndwr Univ Mold Rd Wrexham LL11 2AW Wales

ISBN: (纸本)9781509048151

the paper analyses computational model based on dynamic programming for platforms with multicore processors and heterogeneous architectures with FPGA. the models are applied for solving a canonical problem of dispatching where the computation time significantly depends on the problem scale factor. the parallel algorithms of NP-hard problem of dispatching are complicate and require intensive RAM data exchange. In order to reduce the computation time, it is suggested to use FPGA as a coprocessor providing massively parallel computation and increase the operational performance of the system in one order.

关键词： massively parallel calculations dynamic programming dispatching problem calculations modeling discrete optimisation

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Implementing a space-aware stochastic simulator on low-power architectures: a systems biology case study 25

Implementing a space-aware stochastic simulator on low-power...

引用

25th Euromicro international conference on parallel, Distributed and Network-Based processing (PDP)

作者： Morganti, Lucia Corni, Elena Ferraro, Andrea Cesini, Daniele D'Agostino, Daniele Merelli, Ivan Italian Inst Nucl Phys CNAF Bologna Italy Natl Res Council Italy Inst Appl Math & Informat Technol E Magenes Genoa Italy Natl Res Council Italy Inst Biomed Technol Segrate Mi Italy

ISBN: (纸本)9781509060580

In the last decade, different computing paradigms and modelling frameworks for the description and simulation of biochemical systems based on stochastic modelling have been proposed. From a computational point of view, many simulations of the model are necessary to identify the behaviour of the system. the execution of thousands of simulations can require huge amount of time, therefore the parallelization of these algorithms is highly desirable. In particular, models that consider the size of volumes and objects involved in the reaction are very time-consuming, since many rules should be considered to take into account the position of the different molecules. In this work we present an implementation of a stochastic space-aware simulator which exploits the benefit and features of hybrid low-power computing architectures. this work shows that the simulator dynamic probabilistic approach to select possible chemical reactions can be applied and implemented in hybrid low-power low-cost architectures as well as current industry high-end servers.

关键词： Computational modeling Biological system modeling Stochastic processes Computer architecture Evolution (biology) Biomembranes Power system dynamics

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parallel Symbolic Observation Graph 15

Parallel Symbolic Observation Graph

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15th IEEE international Symposium on parallel and Distributed processing with Applications (ISPA) / 16th IEEE international conference on Ubiquitous Computing and Communications (IUCC)

作者： Ouni, Hiba Klai, Kais Abid, Chiheb Ameur Zouari, Belhassen Univ Tunis El Manar Fac Sci Tunis Tunis 2092 Tunisia Univ Carthage Higher Sch Commun Tunis Mediatron Lab Tunis Tunisia Univ Paris 13 Sorbonne Paris Cite CNRS UMR 7030 LIPN Villetaneuse France

ISBN: (纸本)9781538637906

Model checking is a powerful technique for verifying and analyzing complex systems in many application fields. the analysis process of complex and concurrent systems often requires large computation resources which represents a real challenge. Even with simple configurations, the well-known state explosion problem is faced as the generated state space of such systems grows exponentially with the number of the system components. Numerous methods and techniques have been developed to overcome this problem including parallel and distributed-memory processing. In this paper, we aim at improving the performances of the so called Symbolic Observation Graph (SOG) construction by using parallelization techniques. A SOG is a hybrid structure where the transitions of a system are divided into observed and unobserved ones. the nodes of this graph are then defined as sets of states linked with unobserved transitions (and encoded symbolically with a BDD) and edges are labeled with observed transitions only (and are explicitly represented). We propose two parallel algorithms to build the SOG. the first algorithm is dedicated for shared memory architectures, and is based on the distribution of the SOG construction on several threads using a dynamic load balancing scheme. the second algorithm is proposed for distributed memory architectures, and distributes the SOG construction on processes using a static load balancing scheme. these two algorithms are implemented and their performances are studied and compared to each other and to the sequential construction of the SOG.

关键词： Distributed memory Multi threading parallel model checking Symbolic reachability

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An Optimization and Auto-tuning Method for Scale-free Graph algorithms on SIMD architectures 15

An Optimization and Auto-tuning Method for Scale-free Graph ...

引用

15th IEEE international Symposium on parallel and Distributed processing with Applications (ISPA) / 16th IEEE international conference on Ubiquitous Computing and Communications (IUCC)

作者： Lin, Jie Tan, Yusong Wu, Qingbo Li, Xiaoling Yu, Jie Zhang, Qi Natl Univ Def Technol Coll Comp Changsha Hunan Peoples R China

ISBN: (纸本)9781538637906

the advent of heterogeneous HPC systems, such as the Intel Xeon Phi with many integrated cores and wide SIMD lanes, has been widely used by researchers to accelerate scale-free graph algorithms. However, existing methods are not efficiently considering both the grouping strategy and the selection of the optimizing size for tiling the graph, which would decrease the efficiency of the graph computation. In this paper, we propose a novel Optimization and Auto-Tuning Method on SIMD architecture for scale-free graph algorithms, which is comprised of two sections. Firstly, in the Bucket Grouping Approach, an algorithm-based optimization has been employed to transform the scale-free graph data to conflict-free groups, which can decrease the preprocessing time and improve the SIMD efficiency of scale-free graph applications. Secondly, as optimal tile sizes are changing for different applications of different input graphs, an Auto-Tuning Strategy to optimize tile size achieves effective execution of graph computations. Two typical scale-free graph algorithms, Bellman-Ford and PageRank, are selected to evaluate the performance of OATM. According to the experiment results, OATM performs much better than existing methods, obtaining an average speedup of 1.1x, on these two applications both, by using OATM, comparing to the state-of-the-art methods.

关键词： Bucket grouping Auto-tuning Scale-free graph SIMD architecture

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Inexact matrix exponential preconditioner for implicitly restarted Arnoldi method in fluid dynamics stability problems for parallel heterogeneous architecture 7

Inexact matrix exponential preconditioner for implicitly res...

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7th international conference on Mathematical Modeling in Physical Sciences, IC-MSQUARE 2018

作者： Evstigneev, Nikolay M. Federal Research Center Informatics and Control Institute for System Analysis Russian Academy of Science pr. 60-letiya Oktyabrya 9 Moscow117312 Russia

We wish to solve the problem of linear stability analysis of stationary solutions for a fluid dynamics problem governed by 3D Navier Stokes equations. the discrete problem is of order O(106) - O(107) so we use parallel computations to perform linear analysis. We aim at the heterogeneous computational architecture based on central (CPU) and graphical (GPU) processing units. In the paper we use the implicitly restarted Arnoldi method (IRAM) to recover the most dangerous eigenvalues. the IRAM has poor convergence without specific transformation of the matrix spectrum. Standard methods require either long computations or inverse of the transformed matrix. this can be troublesome in fluid dynamics problems where matrix is not available explicitly and is non-symmetric, ill-conditioned and can be fully filled. We propose the usage of the inexact matrix exponential with shift-inverse transformation using only matrix-vector product. the inverse is performed using Krylov methods using only matrix-vector product. We prove convergence bounds for the GMRES method and show that this type of matrix transformation accelerates GMRES convergence. We demonstrate application of the method in recovering eigenvalues close to the imaginary axis in some model problems on some matrices from the Matrix Market. We also demonstrate the application of the method for some fluid dynamics problems. We demonstrate convergence, acceleration and efficiency on the multiple GPU cluster. © 2018 Institute of Physics Publishing. All rights reserved.

关键词： Inverse problems

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High-Performance Graphics in Racket with DirectX 1

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17th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Bossard, Antoine Kanagawa Univ Grad Sch Sci 2946 Tsuchiya Hiratsuka Kanagawa 2591293 Japan

ISBN: (数字)9783319654829

ISBN: (纸本)9783319654829;9783319654812

Nowadays, modern computer systems rely heavily on parallel processing, and not only because of the multicore CPUs bundled with any machine, even mobile devices, but more and more thanks to the parallel processing capacities of graphics processing units (GPU), general-purpose computing on graphics processing units (GPGPU) being one example. In this paper, relying on the DirectX 12 framework, we propose an innovative approach to enable parallel processing for graphical rendering on both the CPU and GPU for the popular Racket functional programming language (formerly PLT Scheme), and importantly without compromising Racket's usability and programmer-friendliness. Our performance evaluations show significant improvements with respect to execution time (x3 speed-up in some cases), CPU utilisation time (reduced by as much as 80% in some scenarios) and the frame rate when using moving graphics.

关键词： GPU parallel processing Functional Programming Scheme

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