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Enabling semantics to improve detection of data races and misuses of lock-free data structures

Enabling semantics to improve detection of data races and mi...

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Euro-Par conference / 7th international Workshop on Programming Models and Applications for Multicores and Manycores (PMAM) held in conjunction with the 21st SIGPLAN Symposium on Principles and Practice of parallel Programming (PPoPP)

作者： Dolz, Manuel F. Astorga, David Del Rio Fernandez, Javier Torquati, Massimo Garcia, Jose Daniel Garcia-Carballeira, Felix Danelutto, Marco Univ Carlos III Madrid Dept Comp Sci Madrid 28911 Spain Univ Pisa Dept Comp Sci I-56127 Pisa Italy

the rapid progress of multi/many-core architectures has caused data-intensive parallel applications not yet fully optimized to deliver the best performance. In the advent of concurrent programming, frameworks offering structured patterns have alleviated developers' burden adapting such applications to multithreaded architectures. While some of these patterns are implemented using synchronization primitives, others avoid them by means of lock-free data mechanisms. However, lock-free programming is not straightforward, ensuring an appropriate use of their interfaces can be challenging, since different memory models plus instruction reordering at compiler/processor levels can interfere in the occurrence of data races. the benefits of race detectors are formidable in this sense;however, they may emit false positives if are unaware of the underlying lock-free structure semantics. To mitigate this issue, this paper extends threadSanitizer, a race detection tool, with the semantics of 2 lock-free data structures: the single-producer/single-consumer and the multiple-producer/multiple-consumer queues. With it, we are able to drop false positives and detect potential semantic violations. the experimental evaluation, using different queue implementations on a set of benchmarks and real applications, demonstrates that it is possible to reduce, on average, 60% the number of data race warnings and detect wrong uses of these structures.

关键词： data race detectors parallel programming semantics wait- lock-free data structures

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Hardware Acceleration of the Tracking Learning Detection (TLD) Algorithm on FPGA 2017

Hardware Acceleration of the Tracking Learning Detection (TL...

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11th international conference on Distributed Smart Cameras (ICDSC)

作者： Abdali, El Mehdi Hanniche, Abderrahmane Walid Pelcat, Maxime Diguet, Jean-Philippe Berry, Francois Inst Pascal UMR CNRS 6602 Aubiere France Univ Clermont Auvergne Aubiere France INSA Rennes IETR UMR CNRS 6164 Rennes France UMR CNRS 3192 Lab STICC Lorient France

ISBN: (纸本)9781450354875

Robust object tracking is a crucial enabler of many computer vision applications. An embedded object tracker must, in addition to respecting real-time requirements, robustly update the position of the tracked object in the captured images and be able to re-identify the object when it reappears after disappearing for a number of frames. To obtain such a robustness, modern algorithms such as the Tracking Learning Detection (TLD) combine classical tracking techniques with learning capabilities. this combination makes it possible to track an object's displacement, learn its new appearances when it changes orientation and re-identify it once it reappears. the strong performances of these techniques are obtained using costly computation that challenges hardware capabilities in the context of embedded architectures. this paper proposes a strategy for porting the TLD algorithm on an Field-Programmable Gate Array (FPGA). Based on parallel image resizing and selective object patch rejection, the proposed dataflow-oriented strategy demonstrates how the structure of the algorithm can be adapted to be more streaming-oriented and fit the structure of an FPGA. the results prove a tracking performance of up to 160 fps under 50Mhz for VGA images while keeping nearly the tracking robustness of the reference algorithm implementation.

关键词： FPGA Image processing Tracking Learning Detection Dataflow

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Hardware Implementation of the Particle Swarm Optimization Algorithm 24

Hardware Implementation of the Particle Swarm Optimization A...

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24th international conference Mixed Design of Integrated Circuits and Systems (MIXDES)

作者： Talaska, Tomasz Dlugosz, Rafal Pedrycz, Witold UTP Univ Sci & Technol Fac Telecommun Comp Sci & Elect Engn Ul Kaliskiego 7 PL-85796 Bydgoszcz Poland Delphi Poland SA Ul Podgorki Tynieckie 2 PL-30399 Krakow Poland Univ Alberta Dept Elect & Comp Engn Edmonton AB T6G 2V4 Canada

ISBN: (纸本)9788363578121

In this paper, we present a concept of a transistor level implementation of the Particle Swarm Optimization (PSO) algorithm that belongs to the group of unsupervised learning algorithms aimed at the design of artificial neural networks (ANNs). the algorithm exhibits an ability to search for an optimal solution in a multidimensional data space, in which many sub-optimal solutions may exist. the ANN that operates in accordance with the PSO algorithm is composed of a set of cooperating particles (agents) that explore an input data space and communicate information on the best found solution to other particles. the PSO algorithm is usually implemented in software. We in our investigations focus on its transistor level realization. Such an approach enables parallel data processing, in which the overall data rate only moderately depends on the number of particles. Most of the operations and components of such implemented PSO algorithm may be reused considering our former CMOS realizations of other self-organizing learning algorithms. this allowed us to assess main parameters of the PSO.

关键词： Particle Swarm Optimization Algorithm CMOS Artificial Neural Networks Analog signal processing

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ACM international conference Proceeding Series

ACM International Conference Proceeding Series

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7th international conference on Information Communication and Management, ICICM 2017

ISBN: (纸本)9781450352796

the proceedings contain 33 papers. the topics discussed include: low-power parallel data processing using computation reuse;lessons learned and software process improvement;coordination of cloud computing service supply chain with option contracts;an artificial bee colony algorithm for solving the weapon target assignment problem;an approach for identifying the likelihood of an irregular terrain profile being a multipath scattering center in emitter localization;blind audio watermarking by configuring the shape of sorted LWT coefficient magnitudes in synchronous frames;unified connectivity of IoT devices through abstraction of application protocols;conceptual modeling of emergency command and control network;and design of high integrated low phase noise phase-locked loop frequency synthesizer system.

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Greed Is Good: parallel algorithms for Bipartite-Graph Partial Coloring on Multicore architectures

Greed Is Good: Parallel Algorithms for Bipartite-Graph Parti...

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international conference on parallel processing (ICPP)

作者： Mustafa Kemal Taş Kamer Kaya Erik Saule Computer Science and Engineering Sabanci University Istanbul Turkey

In parallel computing, a valid graph coloring yields a lock-free processing of the colored tasks, data points, etc., without expensive synchronization mechanisms. However, coloring is not free and the overhead can be significant. In particular, for the bipartite-graph partial coloring (BGPC) and distance-2 graph coloring (D2GC) problems, which have various use-cases within the scientific computing and numerical optimization domains, the coloring overhead can be in the order of minutes with a single thread for many real-life *** this work, we propose parallel algorithms for bipartite-graph partial coloring on shared-memory architectures. Compared to the existing shared-memory BGPC algorithms, the proposed ones employ greedier and more optimistic techniques that yield a better parallel coloring performance. In particular, on 16 cores, the proposed algorithms are more than 4x faster than their counterparts in the ColPack library which is, to the best of our knowledge, the only publicly-available coloring library for multicore architectures. In addition to BGPC, the proposed techniques are employed to devise parallel distance-2 graph coloring algorithms and similar performance improvements have been observed. Finally, we propose two costless balancing heuristics for BGPC that can reduce the skewness and imbalance on the cardinality of color sets (almost) for free. the heuristics can also be used for the D2GC problem and in general, they will probably yield a better color-based parallelization performance especially on many-core architectures.

关键词： Color Image color analysis Libraries Multicore processing Bipartite graph parallel processing

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ACM international conference Proceeding Series

ACM International Conference Proceeding Series

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10th international conference on Security of Information and Networks, SIN 2017

ISBN: (纸本)9781450353038

the proceedings contain 49 papers. the topics discussed include: models and approaches for the safety and the security of distributed systems;redesign CloudRAID for flexible and secure enterprise file sharing over public cloud storage;a universal user revocation scheme with key-escrow resistant for Ciphertext-policy attribute-based access control systems;an enhanced parallel version of RSA public key crypto based algorithm using OpenMP;a model of a secure electronic voting system based on blind intermediaries using Russian cryptographic algorithms;privacy preserving two-server Diffie-Hellman key exchange protocol;attribute-based approach of defining the secure behavior of automata objects;network security architectures for VANET;tamperproof complex event processing in IoT devices using side channel information;integer overflow vulnerabilities detection in software binary code;a novel malware analysis for malware detection and classification using machine learning algorithms;collaborative representation of Grassmann manifold projection metric for robust multi-spectral face recognition;extended multi-spectral imaging for gender classification based on image set;parameters of the two-stage synchronization algorithm for the quantum key distribution system;abnormal leakage of energy in battery-based IoT-devices;a framework for data security in the cloud using collaborative intrusion detection scheme;and integration of role based access control with homomorphic cryptosystem for secure and controlled access of data in cloud.

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Speed-Up Computational Finance Simulations with OpenCL on Intel Xeon Phi 22nd

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22nd international European conference on parallel and Distributed Computing (Euro-Par)

作者： Papadimitriou, Michail Cramwinckel, Joris Varbanescu, Ana Lucia Delft Univ Technol Delft Netherlands Ortec Finance Rotterdam Netherlands Univ Amsterdam Amsterdam Netherlands

ISBN: (纸本)9783319589435;9783319589428

Computational finance is a domain where performance is in high demand. In this work, we investigate the suitability of Intel Xeon Phi for computational finance simulations. Specifically, we use a scenario based ALM (Asset Liability Management) model and propose a novel OpenCL implementation for Xeon Phi. To further improve the performance of the application, we apply several optimization techniques (data layout and data locality improvement, loop unrolling) and study their effects. Our results show that the optimized OpenCL code deployed on the Phi can run up to 135x faster than the original scalar code running on an Intel i7 GPP. Furthermore, we also show that choosing the optimal work-item/work-group distribution has a compelling effect on massively parallel and heavily-branching code. Overall, these results are significant for the computational finance specialists, as they enable a major increase in model accuracy, because 10x more simulations can be performed in less than a 10th of the original time.

关键词： OpenCL Computing Accelerated architectures Intel Xeon Phi MIC GPGPU parallel computing Asset Liability Management

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Digitizing automotive production lines without interrupting assembly operations through an automatic voxel-based removal of moving objects 13

Digitizing automotive production lines without interrupting ...

引用

13th IEEE international conference on Control & Automation (ICCA)

作者： Schauer, Johannes Nuechter, Andreas Julius Maximilians Univ Wurzburg Informat Robot & Telemat 7 D-97074 Wurzburg Germany

ISBN: (纸本)9781538626795

We present an efficient method to partition a point cloud gathered through kinematic laser scanning into static and dynamic points. the presented algorithm utilizes a voxel grid data structure and uses a ray intersection test to mark voxels as dynamic. the algorithm does not require any ego-motion estimations, computationally expensive object recognition or tracking of moving objects over time. It is easy to implement and can be executed on many cores in parallel. We show the viability of this approach by applying our algorithm to a dataset that we gathered by mounting a FARO Focus3D Laser scanner onto a skid which was then sent along a production line for consumer car chassis in a factory of the Volkswagen corporation. Since factory operators are interested in acquiring digital models of their production lines without suspending factory operations, the resulting point cloud will contain many dynamic objects like humans or other car bodies. We show how our algorithm is able to successfully remove these dynamic objects from the resulting point cloud with minimal errors. Our implementation is published under a free license as part of 3DTK.

关键词： Estimation Field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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Designing a unified architecture graphics processing unit 7

Designing a unified architecture graphics processing unit

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7th international conference on Computer Engineering and Networks, CENet 2017

作者： Wu, Lingjuan Huang, Liang Xiong, Tinggang Wuhan Digital Engineering Institute Wuhan430205 China

Graphics processing Unit (GPU) performs graphics computing and its architecture has developed from the fixed function pipeline to the programmable unified pipeline. Unified architecture promises dynamic load balancing and guarantees the high parallel computing of GPU. this paper presents the design and implementation of a unified architecture GPU. the unified shader is based on the SIMD and SIMT architecture. On the thread level, SIMT guarantees the full-load capability of unified shader by thread managing and scheduling. On the instruction level, SIMD controls the execution of the unified shader hardware unit. We finish the algorithm, architecture design and Verilog RTL implementation. the verification results on FPGA show that the proposed GPU works correctly and its vertex and fragment processing speed reaches one unit per clock cycle. © Copyright owned by the author(s) under the terms of the Creative Commons.

关键词： Graphics processing unit

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Efficient Analysis at Edge 8

Efficient Analysis at Edge

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8th ACM/SPEC international conference on Performance Engineering (ICPE)

作者： Mangels, Tatiana Murarasu, Alin Oden, Forest Fishkin, Alexey Becker, Daniel Siemens AG Corp Technol Otto Hahn Ring 6 Munich Germany

ISBN: (纸本)9781450348997

Digitalization changes traditional business models by using digital technologies to improve existing offerings and to create new offerings. Current technological trends such as artificial intelligence, autonomous systems, and predictive maintenance are ideal candidate technologies to enable digitalization use cases. Often, these technologies rely on the availability of large amounts of data and the capability to process these data efficiently. In contrast to consumer markets, industrial products must fulfill higher non-functional requirements such as fast response times, 24/7 availability and stability, real-time processing, safety, or security requirements. As a consequence, processing capabilities ranging from multicore and manycores to even high end parallel clusters have to be exploited to achieve necessary performance and stability needs. In this paper, we introduce a Distributed Multicore Monitoring Framework (MoMo) which is a reference monitoring solution developed at Siemens Corporate Technology. It can be used to easily build efficient and stable diagnostic solutions which can help to understand the correctness, availability, reliability, and performance of large-scale distributed systems based on live data. Due to its small footprint MoMo can be used to analyze data directly at the data source which, for instance, can significantly reduce the network load. While MoMo's efficiency comes from the usage of multicore processors (CPUs) for running analysis in parallel, its usability is guaranteed by its capability to easily integrate with other monitoring frameworks and its usage of SPL - a domain-specific language which allows user to easily define diagnostic algorithms.

关键词： Monitoring data analysis parallel computing

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