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international conference on VLSI Design

作者： Velamala Pavan Kumar Aravindhan Alagarsamy Department of ECE Centre for Multi-Core Architecture Computation (C-MAC) Koneru Lakshmaiah Education Foundation Vaddeswaram AP India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Blockchain-based cryptocurrency has become extremely popular, especially in various mining approaches and scholarly research. Bitcoin is one of the highest-valued cryptocurrencies mined using many hashing algorithms. the speed and effectiveness of the mining system purely lie in the hash rate and mining board. In view of the mining approach, SHA 256 is one of the most popular and fastest hashing algorithms. In this paper, we propose a high-speed crypto-mining approach using dual SHA256 processing, and the results are compared with various semicustom application-specific integrated circuit (ASIC) architectures. the experimental results indicate an improvement in speed and power consumption of the proposed approach by 6.09% over standard SHA-256 with the Virtex-7 FPGA platform. Similarly, the proposed mining approach significantly improves functional efficiency by 13.40% over the existing hashing architecture. In view of the ASIC platform in comparison with existing hashing architecture, the proposed mining approach offers 13.67% and 16.32% improvement in functional efficiency with 180nm and 90nm respectively.

关键词： Hands Power demand Embedded systems Bitcoin Very large scale integration throughput Field programmable gate arrays Standards Pipeline processing

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A High-Speed Multiplier Design Using 2—Bit Reordering 4:3 Counter in a Wallace Tree Structure

A High-Speed Multiplier Design Using 2—Bit Reordering 4:3 C...

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international conference on Trends in Electronics and Informatics (ICEI)

作者： Saleem Syed Abdul Khader Khaderabad Sahithi Ankirapalli Swathi Lingamgunta Sasi Priyanka thammisetty Jaffar Ali Syed Dept. of Electronics and Communication Engineering Annamacharya Institute of Technology and Sciences Kadapa India

ISBN: (数字)9798331544607

ISBN: (纸本)9798331544614

It is known that the multiplier is widely applied, and to produce the outputs for the next stage, there is a reliance on the previous stage. Due to this, the multiplication process takes time to complete. As the binary bit counts of the multiplier and multiplicand increase, it takes longer to generate the output. this longer delay can severely impair the overall performance of digital systems, especially in applications requiring high-speed computations. therefore, optimizing the Multiplier for both speed and power efficiency is crucial to enhancing the performance of modern computing architectures. To achieve this optimization, various techniques such as parallel processing and reduced gate counts can be employed. Moreover, utilising advanced algorithms and hardware accelerators can enhance the efficiency of these multipliers in challenging computational settings. this will affect the circuit performance. A new technique known as the reordering technique is implemented in this project to enhance the multiplier in terms of speed and efficiency. this method is implemented by separating the high-state bits from the low-state bits using the reordering circuit, and then the separated bits are processed in the usual manner. this helps in the reduction of critical path latency, which benefits by enhancing the circuit's power consumption as less power is being released as heat or another form.

关键词： Micromechanical devices Power demand Logic gates parallel processing Market research Delays Table lookup Informatics Adders Optimization

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30th international conference on parallel and Distributed processing Techniques, PDPTA 2024, held as part of the World Congress in Computer Science, Computer Engineering and Applied Computing, CSCE 2024

30th International Conference on Parallel and Distributed Pr...

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30th international conference on parallel and Distributed processing Techniques, PDPTA 2024, held as part of the World Congress in Computer Science, Computer Engineering and Applied Computing, CSCE 2024

ISBN: (纸本)9783031856372

the proceedings contain 24 papers. the special focus in this conference is on parallel and Distributed processing Techniques. the topics include: parallel N-Body Performance Comparison: Julia, Rust, and More;REFT: Resource-Efficient Federated Training Framework for Heterogeneous and Resource-Constrained Environments;An Efficient Data Provenance Collection Framework for HPC I/O Workloads;using Minicasts for Efficient Asynchronous Causal Unicast and Byzantine Tolerance;a Comparative Study of Two Matrix Multiplication algorithms Under Current Hardware architectures;Is Manual Code Optimization Still Required to Mitigate GPU thread Divergence? Applying a Flattening Technique to Observe Performance;towards Automatic, Predictable and High-Performance parallel Code Generation;Attack Graph Generation on HPC Clusters;analyzing the Influence of File Formats on I/O Patterns in Deep Learning;inference of Cell–Cell Interactions through Spatial Transcriptomics Data Using Graph Convolutional Neural Networks;natural Product-Like Compound Generation with Chemical Language Models;improved Early–Modern Japanese Printed Character Recognition Rate with Generated Characters;Improved Method for Similar Music Recommendation Using Spotify API;Reconfigurable Virtual Accelerator (ReVA) for Large-Scale Acceleration Circuits;Building Simulation Environment of Reconfigurable Virtual Accelerator (ReVA);vector Register Sharing Mechanism for High Performance Hardware Acceleration;Efficient Compute Resource Sharing of RISC-V Packed-SIMD Using Simultaneous Multi-threading;introducing Competitive Mechanism to Differential Evolution for Numerical Optimization;hyper-heuristic Differential Evolution with Novel Boundary Repair for Numerical Optimization;jump Like a Frog: Optimization of Renewable Energy Prediction in Smart Gird Based on Ultra Long Term Network;vision Transformer-Based Meta Loss Landscape Exploration with Actor-Critic Method;Fast Computation Method for Stopping Condition of Range Restricted

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Data Center Infrastructure in the Era of Generative Artificial Intelligence

Data Center Infrastructure in the Era of Generative Artifici...

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Innovative Research in Applied Science, Engineering and Technology (IRASET),conference on

作者： Antonio Cortés Castillo Departamento de Informática Universidad de Panamá Ciudad de Panamá Panamá

ISBN: (数字)9798331532970

ISBN: (纸本)9798331532987

Nowadays, Generative Artificial Intelligence (GenAI) is increasingly making inroads in Data Centers, helping to improve aspects related to latency and high speed. Data center-level network infrastructures require managing large volumes of data using high-speed protocols such as InfiniBand, as it allows low latency and parallel processing, as well as various applied switches at different network architecture levels. In this article, we examine those protocols at the data communication level that GenAI uses to optimize and guarantee data flow between nodes, as well as the design and reference of network architectures in the field of GenIA. On the other hand, the components of the GenAI networks used are analyzed. Similarly, a case study is proposed where the performance of the Graphic processing Units (GPUs) is analyzed based on the definition of a series of metrics such as memory access, memory bandwidth, throughput, energy consumption, temperature, and clock speed, and that through the simulation of neural networks specifically using the Radial Basic Function (RBF) and Multilayer Perceptron (MLP) algorithms, it helps to understand and analyze to what extent these metrics behave and generate possible solutions in the field of data centers.

关键词： Measurement Data centers Protocols Generative AI Optical switches Memory management Graphics processing units Bandwidth throughput Servers

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Profiler: An Exploration of Micro-Architecture-Oblivious GPU Program Characteristics Profiling and Analysis Framework

Profiler: An Exploration of Micro-Architecture-Oblivious GPU...

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Software Engineering and Computer Science (CSECS), international conference on

作者： Wang Peng Qi Kaiyuan Zhang Dong Liu Peng dept. Cloud Computing R&D Inspur Group Co. Ltd Jinan Inspur Data Technology Co. Ltd Jinan China

ISBN: (数字)9798331522216

ISBN: (纸本)9798331522223

Given the swift advancements in GPU architectures, the process of assessing and improving GPU rendering performance has grown increasingly sophisticated and vital. To address these challenges and provide microarchitecture-agnostic insights, this paper introduces MICPAT, a tool for GPU characteristic profiling. MICPAT extracts key program characteristics such as instruction composition, basic block count, instruction frequency and memory allocation size across NVIDIA's Kepler, Maxwell, Pascal, and Volta GPU series. By analyzing these microarchitecture-agnostic characteristics, developers gain deep insights into the behavior and performance of their GPU programs. MICPAT supports precompiled applications utilizing CUDA, OpenACC, OpenCL, or CUDA Fortran. Serving as a versatile platform, MICPAT enables consistent analysis across this diverse set of GPU architectures and precompiled application environments. Utilizing Octane renderer, as well as Rodinia and Parboil benchmarks, extensive experimental evaluations across 100 GPU rendering applications have validated MICPAT's efficacy and its microarchitecture-agnostic nature. the open source repo is https://***/records/13623324.

关键词： Computer science Microarchitecture Graphics processing units Computer architecture Organizations Benchmark testing Rendering (computer graphics) Resource management Software engineering Radio spectrum management

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Research of Different Neural Network architectures for Real-Time Metal Surface Defect Detection

Research of Different Neural Network Architectures for Real-...

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international Youth conference on Radio Electronics, Electrical and Power Engineering (REEPE)

作者： Ye Zheming Valery I. Terekhov Jin He Bauman Moscow State Technical University Moscow Russian Federation

ISBN: (数字)9798331531836

ISBN: (纸本)9798331531843

this paper explores the application of various deep learning-based detection networks in the field of metal surface defect detection. the study focuses on the performance comparison of three neural networks: Faster Region-based Convolutional Neural Network (Faster R-CNN), You Only Look Once (YOLO), and Single Shot MultiBox Detector (SSD). the well-known Northeastern University Metal Surface Defect (NEU-DET) dataset is used to evaluate the models in terms of accuracy and speed. Although Faster R-CNN exhibits superior accuracy, it does not cope with real-time detection due to its slow processing speed. In contrast, YOLOv7(an enhanced version of YOLO) demonstrates high efficiency and speed, particularly for large object detection, making it the optimal choice for real-time defect detection tasks. Future work will focus on optimizing YOLOv7 for better detection accuracy on small objects and complex backgrounds to enhance its industrial applicability.

关键词： YOLO Power engineering Accuracy Neural networks Metals Detectors Real-time systems Surface treatment Optimization Defect detection

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Developing Predictive Models and GUI for Area & Power Estimation of PISO Shift Register for FPGAs

Developing Predictive Models and GUI for Area & Power Estima...

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international conference on Signal processing and Communication (ICSC)

作者： Radhika Gupta Priti Kumari Rashi Jaiswal Tukur Gupta Department of Electronics & Communication Engineering Ajay Kumar Garg Engineering College Ghaziabad India

ISBN: (数字)9798331511890

ISBN: (纸本)9798331511906

Shift registers with parallel-In Serial-Out (PISO) functionality are essential components in digital electronics. they ease data transmission and minimize the amount of wiring needed by converting parallel data into a serial format, and hence used in digital communications, signal processing, and data storage. the significance of these shift registers and their guiding principles is anticipated to grow as digital technology develops, highlighting the need for a thorough analysis of their design constraints. Hence, area and power being two main design constraints for digital circuits need to be estimated. these estimates can be made using current commercial tools, however doing so requires more time because full design cycles must be followed. therefore, challenges for designers lie in accurate estimation of resource utilization and power dissipation at the early stages of designing while working under a tight deadline. this paper develops area and power estimation models for PISO shift register circuit using the curve fitting and regression technique in MATLAB. Vivado Design Suite (2014.4) is used to simulate and synthesize these circuits for various input/output (I/O) configurations targeted to Zynq-family Field-Programmable Gate Array (FPGA) device (xc7z020clg484-1). Furthermore, a user-friendly graphical user interface (GUI) is developed using Python Tkinter prompting designers to enter minimum input parameters and providing quick estimates of look-up tables (LUTs), flip-flops (FFs) and total on-chip power. these values predicted using GUI are compared with those obtained using Vivado tool. Comparison results infer that estimation errors lie in a comparable range. Hence, the proposed models and GUI expedite the design process by early and accurate estimation of area and power for FPGA-based PISO shift registers.

关键词： Machine learning algorithms Signal processing algorithms Predictive models Shift registers Prediction algorithms Table lookup Resource management Integrated circuit modeling Field programmable gate arrays Graphical user interfaces

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RenderMiner: Mining Micro-Architecture Characteristics of Rendering Programs on GPGPU

RenderMiner: Mining Micro-Architecture Characteristics of Re...

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Software Engineering and Computer Science (CSECS), international conference on

作者： Peng Wang Kaiyuan Qi Dept. Cloud Computing Research and Development Inspur Group Co. Ltd Jinan Inspur Data Technology Co. Ltd Jinan China

ISBN: (数字)9798331522216

ISBN: (纸本)9798331522223

In recent years, page-table the applications of virtual reality, augmented reality and mixed reality have become more and more popular, all of which are essentially image rendering. Graphics rendering requires a lot of calculations to determine the rendering parameters of each pixel. However, how to reveal the micro-architecture characteristics of GPGPU to help architects increase optimization opportunities and improve the performance of microprocessors becomes imperative. In this article, we propose RenderMiner, a framework which comprehensively characterizes the GPGPU rendering programs at the instruction and memory levels. Specifically, we design instruction mix based on the SASS instruction set, instruction frequency, register reuse distribution and memory call stack to efficiently depict the micro-architecture characteristics of rendering programs and compare with the non-rendering programs. We use RenderMiner to analyze the inherent behaviors of rendering programs combined with machining learning methods through 60 CPU rendering programs, 34 GPU rendering programs, 52 GPU non-rendering programs such as Rodinia and Parboil, and some real-world workloads, such as V-Ray5 Benchmark, Blender, Octane and Kobra Vulkan. After analysis of the rendering programs and comparison with non-rendering programs and the real-world workloads, the key findings of our conclusion are as following: (1) the instruction mix of CPU rendering programs is totally different from that of MiBench, especially at the aspect of arithmetic operation, memory read, memory write and control flow. (2) the instruction-level parallel interval of the CPU rendering program is mainly concentrated from 3 to 6. (3) there is comparable instruction frequency among GPU rendering, Octane, Kobra vulkan and non-rendering programs. (4) the average total instruction count of GPU rendering programs is 355 times more than that of non-rendering programs. (5) the portion of floating point of GPU rendering programs, B

关键词： Time-frequency analysis Graphics processing units Mixed reality parallel processing Benchmark testing Rendering (computer graphics) Real-time systems Registers Optimization Software engineering

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parallel architectures for image processing

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ELECTRONICS & COMMUNICATION ENGINEERING JOURNAL 1998年第3期10卷 139-151页

作者： Downton, A Crookes, D Univ Essex Dept Elect Syst Engn Colchester CO4 3SQ Essex England Queens Univ Belfast Dept Comp Sci Belfast BT7 1NN Antrim North Ireland

Image processing is often considered a good candidate for the application of parallel processing because of the large volumes of data and the complex algorithms commonly encountered. this paper presents a tutorial introduction to the field of parallel image processing. After introducing the classes of parallel processing a brief review of architectures for parallel image processing is presented. Software design for low-level image processing and parallelism in high-level image processing are discussed and an application of parallel processing to handwritten postcode recognition is described. the paper concludes with a look at future technology and market trends.

关键词： image processing image recognition parallel architecture Digital signal processing chips software design Microprocessors and microcomputers parallel architectures handwritten postcode recognition Optical information, image and video signal processing digital signal processing chips optical character recognition Computer vision and image processing techniques high-level image processing low-level image processing parallel processing

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How to parallelize cellular neural networks on cluster architectures

How to parallelize cellular neural networks on cluster archi...

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7th international Symposium on parallel architectures, algorithms and Networks (I-SPAN 2004)

作者： Weishäupl, T Schikuta, E Univ Vienna Dept Comp Sci & Business Informat A-1010 Vienna Austria

ISBN: (纸本)0769521355

In this paper we present "Rules of thumb" for the efficient and straight-forward parallelization of Cellular Neural Networks (CNNs) processing image data on cluster architectures. the rules result from the application and optimization of the simple but effective structural data parallel approach, which is based on the SPMD model. Digital gray-scale images were used to evaluate the optimized parallel cellular neural network program. the process of parallelizing the algorithm employs HPF to generate an MPI-based program.

关键词： Cellular neural networks

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