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Problem representations for an automatic mapping algorithm on heterogeneous processing environments 7

Problem representations for an automatic mapping algorithm o...

1993 Workshop on Heterogeneous processing, VVHP 1993, Held in conjunction with the 7th international parallel processing Symposium

作者： Leangsuksun, Chokchai Potter, Jerry Department of Mathematics and Computer Sciences Kent State University KentOH44242 United States

ISBN: (纸本)0818635312

We presents two heterogeneous processing (HP) problem representations that are 1) a program representation called a "Meta Graph" and 2) a targeted HP hardware configuration representation called an "Architecture Graph". these representations are inputs to an automatic mapping algorithm for HP environments [18]. the paper discusses the definitions of the proposed representations and initial experimental results. © 1993 IEEE.

关键词： Conformal mapping

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parallel implementation of logical analysis of data (LAD) for discriminatory analysis of protein mass spectrometry data

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6th international conference on parallel processing and applied mathematics

作者： Puszynski, Krzysztof Silesian Tech Univ Katowice Poland

ISBN: (纸本)3540341412

A parallel implementation of proteomic ovarian cancer diagnosis system based on logical analysis of data is shown. the implementation is based on computational cluster elaborated in System Engineering Group at Silesian University of Technology. For verification of algorithm and software Ovarian Dataset 8-7-02 (which can be found at http://***) was used. this mass spectrometry data contains intensity levels of 15 154 peptides defined by their mass/charge ratios (m/z) in serum of 162 ovarian cancer and 91 control cases. A Seti-like and OpenMosix with PVM cluster technology was used to construct in LAD a fully reproducible models (1) using full range and (2) using only 700-12000 of m/z values of peptides and proved in multiple cross-validation leave-one-out tests to guarantee sensitivities and specificities of up to 100%.

关键词： parallel processing systems

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parallel Stochastic Search for PAPR Reduction of OFDM Signal 7

Parallel Stochastic Search for PAPR Reduction of OFDM Signal

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Joint 7th international conference on Soft Computing and Intelligent Systems (SCIS) and 15th international Symposium on Advanced Intelligent Systems (ISIS)

作者： Shigei, Noritaka Kumashiro, Hideaki Miyajima, Hiromi Kagoshima Univ 1-21-40 Korimoto Kagoshima 8900065 Japan

ISBN: (纸本)9781479959556

Tone injection (TI) is an effective technique to overcome high PAPR (peak-to-average power ratio) of OFDM. the PAPR reduction problem solved with TI is a combinatorial problem. Although the effectiveness of GA has been demonstrated for this problem, GA involves relative complex operators. this implies that, when implementing the methods of TI on digital circuits, other methods may outperform GA under the same processing time. In this paper, we investigate effective parallel search methods for the PAPR reduction, which are of simple structure for implementing digital circuits. At first, as the basis of the parallel methods, we propose two types of stochastic search methods. the one is Flip-Probability-specified type (FP) search and the other is a specified-Number-of-Flips type (NF) search. Both of them use only simple stochastic operators. then, we propose an effective digital circuit implementation of the solution evaluation function. Finally, we propose a parallel search method based on FP and NF search. the simulation results show that, the proposed parallel search methods can improve not only the processing speed but also the quality of the solution.

关键词： OFDM modulation combinatorial mathematics digital circuits genetic algorithms radiocommunication search problems stochastic processes stochastic programming telecommunication computing FP search GA NF search OFDM signal PAPR reduction TI combinatorial problem digital circuit implementation flip-probability-specified type search genetic algorithm orthogonal frequency division multiplexing parallel stochastic search method peak-to-average power ratio specified-number-of-flip type search tone injection wireless communication Digital circuits Genetic algorithms Noise measurement Peak to average power ratio Search methods Simulation

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Performance of Scalable Off-the-Shelf Hardware for Data-intensive parallel processing using MapReduce

Performance of Scalable Off-The-Shelf Hardware for Data-inte...

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7th international conference on Computing and Convergence Technology (ICCCT)

作者： Fadzil, Ahmad Firdaus Ahmad Khalid, Noor Elaiza Abdul Manaf, Mazani Univ Teknol MARA UiTM Fac Comp & Math Sci Shah Alam Malaysia

ISBN: (纸本)9781467308946;9788994364261

Large data and information processing requires high processing power that usually involve supercomputers which are costly. MapReduce parallel framework introduces an automated way of distributing these large processes to many computers. this paper proposes to conduct preliminary studies on scalability using MapReduce as an automated parallel processing running on low-cost off-the-shelf hardware. the system architecture is built with collections of off-the-shelf hardware. the scalability test will be conducted by adding an off-the-shelf hardware one at a time to the architecture. MapReduce tool is used as a parallel framework to automatically distribute tasks according to available resources. Performance will be evaluated based on improvement in speedup. It is found that MapReduce is able to accommodate scalability of off-the-shelf hardware resources by automatically distributing tasks regardless of the number of hardware being added to the architecture.

关键词： MapReduce parallel processing Off-the-shelf hardware scalability

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parallel explicit finite element dynamics with nonlocal constitutive models

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COMPUTERS & STRUCTURES 2001年第26-28期79卷 2287-2297页

作者： Patzák, B Rypl, D Bittnar, Z Czech Tech Univ Fac Civil Engn Prague 16629 Czech Republic

the present paper deals with the parallelization of an explicit time stepping algorithm in a general finite element environment. Particular attention has been paid to nonlocal constitutive models. A central difference method has been used to discretize the governing equations in time. Modifications of both node-cut and element-cut strategies have been developed to provide an efficient support for nonlocal constitutive models. Efficiency of the proposed approach is demonstrated on different hardware platforms. (C) 2001 Civil-Comp Ltd. and Elsevier Science Ltd. All rights reserved.

关键词： parallel processing explicit dynamics nonlocal models

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A novel approach for performance improvement in parallel processing 7

A novel approach for performance improvement in parallel pro...

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7th international Multi-conference on Complexity, Informatics and Cybernetics, IMCIC 2016 and 7th international conference on Society and Information Technologies, ICSIT 2016

作者： Ananth Prabhu, G. Aithal, Ganesh Ahammed, G.F. Ali Tale, Sarika Basthikodi, Mustafa Department of CSE SCEM Mangalore India MITE Mangalore India Department of CSE VTU PG CENTRE Mysore India Department of DECS VIAT Muddenahalli India Department of CSE BIT Mangalore India

ISBN: (纸本)9781941763346

With the high requirements of gene sequencing in the field of scientific research, it is essential to make faster sequencing process. the one of the main sequencing operation is done using Smith Waterman algorithm. this algorithm is used in two conventional ways to evaluate the matrix elements. they are i. Sequential processes ii. Conventional parallel processes. Sincethe work is to consider these both of these approaches and evolve a new so that these there are three main objectives are met a) Should take less time for the computation of the matrix elements b) optimize the processor used. Even though later one conventional parallel (O(2m)) is faster than the former one sequential processing O(2mn), this work tried an attempt for reducing the timing still further, with a challenge to reduce to an extent of O(m) by introducing cross diagonal element wise parallel processing approach. Also as a part of the work processor optimization of the processor for the conventional parallel and the cross diagonal element wise parallel approach is completed with a satisfactory result. the Cross Diagonal Element Wise parallel processing Approach (CDEWPPA) performs better than the conventional parallel approach for the query execution time test as well as for the speed up ratio.

关键词： Genes

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parallel tiled QR factorization for multicore architectures

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7th international conference on parallel processing and applied mathematics

作者： Buttari, Alfredo Langou, Julien Kurzak, Jakub Dongarra, Jack Univ Tennessee Dept Comp Sci Knoxville TN 37996 USA Univ Tennessee Dept Elect Engn Knoxville TN 37996 USA Univ Colorado Dept Mech Sci Denver CO 80309 USA Univ Colorado Health Sci Ctr Denver CO 80309 USA Oak Ridge Natl Lab Comp Sci & Mech Div Oak Ridge TN USA Univ Manchester Manchester M13 9PL Lancs England

ISBN: (纸本)9783540681052

As multicore systems continue to gain ground in the High Performance Computing world, linear algebra algorithms have to be reformulated or new algorithms have to be developed in order to take advantage of the architectural features on these new processors. Fine grain parallelism becomes a major requirement and introduces the necessity of loose synchronization in the parallel execution of an operation. this paper presents an algorithm for the QR factorization where the operations can be represented as a sequence of small tasks that operate on square blocks of data. these tasks can be dynamically scheduled for execution based on the dependencies among them and on the availability of computational resources. Compared to the standard approach, say with LAPACK, may result in an out of order execution of the tasks which will completely hide the presence of intrinsically sequential tasks in the factorization. Performance comparisons are presented with the LAPACK algorithm for QR factorization where parallelism can only be exploited at the level of the BLAS operations.

关键词： Factorization

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Practical Implementation of Precoding Technologies in High-speed Optical Transmission

Practical Implementation of Precoding Technologies in High-s...

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7th international conference on the Optical Internet

作者： Sugihara, Takashi Mitsubishi Electr Corp Informat Technol R&D Ctr Kanagawa 2478501 Japan

A novel architecture of the precoding is proposed for pre-distortion based transmitters. To reduce the circuit complexity, we introduce a parallel prefix network based a DQPSK precoder, a flip-flop based look up table... 详细信息

ISBN: (纸本)9784885522307

关键词： Optical fiber dispersion optical modulation optical transmitters signal processing

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Topology preserving 2-subfield 3D thinning algorithms

Topology preserving 2-subfield 3D thinning algorithms

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7th IASTED international conference on Signal processing, Pattern Recognition and Applications, SPPRA 2010

作者： Németh, Gábor Kardos, Péter Palágyi, Kálmán Dept of Image Processing and Computer Graphics University of Szeged Szeged Hungary

ISBN: (纸本)9780889868236

this paper presents a new family of 3D thinning algorithms for extracting skeleton-like shape features (i.e, centerline, medial surface, and topological kernel) from volumetric images. A 2-subfield strategy is applied: all points in a 3D picture are partitioned into two subsets which are alternatively activated. At each iteration, a parallel operator is applied for deleting some border points in the active subfield. the proposed algorithms are derived from Ma's sufficient conditions for topology preservation, and they use various endpoint characterizations.

关键词： three dimensional

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Vedic-based squaring circuit using parallel prefix adders 7

Vedic-based squaring circuit using parallel prefix adders

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7th international conference on Signal processing and Integrated Networks, SPIN 2020

作者： Jain, Avinash Bansal, Somya Akhter, Shamim Khan, Shaheen Jaypee Institute of Information Technology Department of Electronics and Communication Engineering Noida India Mewat Engineering College Department of Electronics and Communication Engineering Haryana India

ISBN: (纸本)9781728154756

this paper proposes a novel method using Vedic mathematics for calculating the square of binary numbers. An improved Vedic multiplier architecture is used in the binary squaring circuit. the circuit is further improved by using parallel prefix adder. parallel prefix adder provides the best delay performance at the expense of area overhead. In this work, the parallel prefix adders like Kogge-Stone adder, Brent-Kung adder, Sklansky adder, Ladner-Fischer adder and Han-Carlson adder are used. the circuit is designed in Verilog HDL. the circuit synthesis has been performed in Xilinx ISE 14.7. Simulation has been performed for 4-bit and 8-bit designs. Performance comparison has been performed taking into consideration several parameters measured on different FPGA families. An improved speed performance is observed in this paper when compared with the previously reported circuits. © 2020 IEEE.

关键词： Timing circuits

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