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An Evaluation of Misaligned Data Access Handling Mechanisms in Dynamic Binary Translation Systems 09

An Evaluation of Misaligned Data Access Handling Mechanisms ...

引用

7th international symposium on code generation and optimization

作者： Li, Jianjun Wu, Chenggang Hsu, Wei-Chung Chinese Acad Sci Inst Comp Technol Key Lab Comp Syst & Architecture Beijing Peoples R China Univ Minnesota Dept Comp Sci Minneapolis MN 55455 USA

ISBN: (纸本)9780769535760

Binary translation (BT) has been an important approach to migrate application software across instruction set architectures (ISAs). Some architectures, such as X86, allow misaligned data accesses (MDAs), while most modern architectures have the alignment restriction that requires data to be aligned in memory on natural boundaries. In a binary translation system, where the source ISA allows MDA and the target ISA does not, memory operations must be carefully translated to satisfy the alignment restriction. Naive translation will cause frequent misaligned data access traps to occur at runtime on the target machine, and severely slow down the migrated application. this paper evaluates different approaches in handling MDA in binary translation systems. It also proposes a new mechanism to deal with MDAs. Measurements based on SPEC CPU2000 and CPU2006 benchmark show that the proposed approach can significantly outperform existing methods.

关键词： optimization misaligned memory access binary translation

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Automatic Feature generation for Machine Learning Based Optimizing Compilation 09

Automatic Feature Generation for Machine Learning Based Opti...

引用

7th international symposium on code generation and optimization

作者： Leather, Hugh Bonilla, Edwin O'Boyle, Michael Univ Edinburgh Sch Informat Edinburgh Midlothian Scotland

ISBN: (纸本)9780769535760

Recent work has shown that machine learning can automate and in some cases outperform hand crafted compiler optimizations. Central to such an approach is that machine learning techniques typically rely upon summaries or features of the program. the quality of these features is critical to the accuracy of the resulting machine learned algorithm;no machine learning method will work well with poorly chosen features. However, due to the size and complexity of programs, theoretically there are an infinite number of potential features to choose from. the compiler writer now has to expend effort in choosing the best features from this space. this paper develops a novel mechanism to automatically find those features which most improve the quality of the machine learned heuristic. the feature space is described by a grammar and is then searched with genetic programming and predictive modeling. We apply this technique to loop unrolling in GCC 4.3.1 and evaluate our approach on a Pentium 6. On a benchmark suite of 57 programs, GCC's hard-coded heuristic achieves only 3% of the maximum performance available, while a state of the art machine learning approach with hand-coded features obtains 59%. Our feature generation technique is able to achieve 76% of the maximum available speedup, outperforming existing approaches.

关键词： Machine learning Optimizing compilers Machine learning algorithms Humans Program processors Informatics Learning systems Genetic programming Predictive models Tree data structures

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Parameter space dimension reduction for multidimensional signals differential pulse-code modulation interpolator 7

Parameter space dimension reduction for multidimensional sig...

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7th international symposium on Digital Forensics and Security (ISDFS)

作者： Maksimov, Aleksey Gashnikov, Mikhail Samara Natl Res Univ Dept GIS & ITsec Samara Russia RAS IPSI RAS Branch FSRC Crystallog & Photon MMIP Lab Samara Russia

ISBN: (纸本)9781728128276

In this paper, new parameterized differential pulse-code modulation interpolator is proposed. It uses the correspondence of signal samples in the processed sample vicinity to select the interpolation method. Interpolation error of proposed interpolator is minimized during the optimization procedure. Before the optimization, the parameter range dimension is reduced in order to lower the computational complexity. Experimental research shows that proposed interpolator outperforms the non-parameterized one

关键词： multidimensional signal interpolation differential pulse-code modulation parameterization dimension reduction adaptability

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An optimization Approach for Designing Multilevel Converters 7

An Optimization Approach for Designing Multilevel Converters

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7th IEEE international symposium On Power Electronics for Distributed generation Systems (PEDG)

作者： Di Tullio, Luccas Arefifar, Seyed Ali Ordonez, Martin Univ British Columbia Dept Elect & Comp Engn Vancouver BC Canada

ISBN: (纸本)9781467386173

optimization techniques have become powerful tools in the design of power electronics converters. In this paper an optimization technique is proposed to design a multilevel converter. Unlike the majority of previous converter optimization, this technique considers multiple characteristics to be optimized. Efficiency, inductance, loss distribution and component cost are optimized through a weighted objective function. the technique selects between the NPC and the ANPC topologies as each presents key advantages at specific conditions. A model to calculate the switching and conduction losses and the loss distribution for each topology was derived. the semiconductor technology is not restrained to a single type. Instead IGBTs, MOSFETs, and diodes are considered along with the switching frequency. the optimization is carried out for both inverter and rectifier operation, both with three loading conditions. As expected, some key characteristics of the topology and semiconductor become pronounced as conditions vary, resulting significantly different optimal designs.

关键词： Topology

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Tailoring graph-coloring register allocation for runtime compilation 06

Tailoring graph-coloring register allocation for runtime com...

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4th international symposium on code generation and optimization

作者： Cooper, Keith D. Dasgupta, Anshurnan Rice Univ Houston TX 77251 USA

ISBN: (纸本)0769524990

Just-in-time compilers are invoked during application execution and therefore need to ensure fast compilation times. Consequently, runtime compiler designers are averse to implementing compile-time intensive optimization algorithms. Instead, they tend to select faster but less effective transformations. In this paper we explore this trade-off for an important optimization - global register allocation. We present a graph-coloring register allocator that has been redesigned for runtime compilation. Compared to Chaitin-Briggs [7], a standard graph-coloring technique, the reformulated algorithm requires considerably less allocation time and produces allocations that are only marginally worse than those of Chaitin-Briggs. Our experimental results indicate that the allocator performs better than the linear-scan and Chaitin-Briggs allocators on most benchmarks in a runtime compilation environment. By increasing allocation efficiency and preserving optimization quality, the presented algorithm increases the suitability and profitability of a graph-coloring register allocation strategy for a runtime compiler.

关键词： Optimizing compilers Runtime environment Design optimization Java Virtual machining Algorithm design and analysis Profitability Program processors Virtual manufacturing Costs

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On N-detect pattern set optimization 06

On N-detect pattern set optimization

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7th international symposium on Quality Electronic Design

作者： Huang, Yu Mentor Graph Corp Marlborough MA 01752 USA

ISBN: (纸本)0769525237

In this paper, we illustrate that the traditional N-detect ATPG is unoptimized in terms of the size of the generated pattern set. the optimization problem is formulated as a minimum covering problem. Integer Linear Programming (ILP) is applied to obtain an N-detection ATPG pattern set with the minimum number of patterns. A heuristic method is also proposed to obtain sub-optimal solutions efficiently. Experimental results demonstrate that by using the proposed method, the number of N-detection patterns can be reduced by about 18% for N=3 and about 13% for N=5 without compromising N-detection objective.

关键词： Automatic test pattern generation Testing Circuit faults Fault detection Compaction optimization methods Iterative algorithms Graphics Integer linear programming Very large scale integration

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A Practical Approach to Hardware Performance Monitoring based Dynamic optimizations in a Production JVM 09

A Practical Approach to Hardware Performance Monitoring base...

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7th international symposium on code generation and optimization

作者： Cuthbertson, John Viswanathan, Sandhya Bobrovsky, Konstantin Astapchuk, Alexander Kaczmarek, Eric Srinivasan, Uma Intel Corp Managed Runtime Technol Ctr Santa Clara CA 95052 USA Intel Corp Managed Runtime Technol Ctr Novosibirsk Russia Intel Corp Managed Runtime Technol Ctr Hillsboro OR 97124 USA

ISBN: (纸本)9780769535760

While the concept of online profile directed dynamic optimizations using hardware performance monitoring unit (PMU) data is not new, it has seen fairly limited or no use in commercial JVMs. the main reason behind this fact is the set of significant challenges involved in (7) obtaining low overhead and usable profiling support from the underlying platform (2) the complexity of filtering, interpreting and using precise PMU events online in a JVM environment (3) demonstrating the total runtime benefit of PMU data based optimizations above and beyond regular online profile based optimizations. In this paper we address all three challenges by presenting a practical framework for PMU data collection and use within a high performance product JVM on a highly scalable server platform. Our experiments with Java (TM) workloads using the Sun (TM) Hotspot (TM) JDK 1.6 JVM on the Intel Itanium platform indicate that the hardware data collection overhead (less than 0.5%) is not as significant as the challenge of extracting the precise information for optimization purposes. We demonstrate the feasibility of mapping the instruction IP address based hardware event information to the runtime components as well as the AT server compiler internal data structures for use in optimizations within a dynamic environment. We also evaluated the additional performance potential of optimizations such as object co-location during garbage collection and global instruction scheduling in the AT compiler with the use of PMU generated load latency information. Experimental results show performance improvements of up to 14% with an average of 2.2% across select Java server benchmarks such as SPECjbb2005[16], SPECjvm2008[17] and Dacapo[18]. these benefits were observed over and above those provided by profile guided server JVM optimizations in the absence of hardware PMU data.

关键词： optimization Java Hardware Performance Monitoring

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COLE: Compiler optimization Level Exploration 08

COLE: Compiler Optimization Level Exploration

引用

6th international symposium on code generation and optimization

作者： Hoste, Kenneth Eeckhout, Lieven Univ Ghent ELIS Dept B-9000 Ghent Belgium

ISBN: (纸本)9781595939784

Modern compilers implement a large number of optimizations which all interact in complex ways, and which all have a different impact oil code quality, compilation time, code size, energy consumption, etc. For this reason, compilers typically provide a limited number of standard optimization levels, such as -01, -02, -03 and -0s, that combine various optimizations providing a number of trade-offs between multiple objective functions (such as code quality, compilation time and code size). the construction of these optimization levels, i.e., choosing which optimizations to activate at each level, is a manual process typically done using high-level heuristics based on the compiler developer's experience. this paper proposes COLE, Compiler optimization Level Exploration, a framework or automatically finding Pareto optimal optimization levels through multi-objective evolutionary searching. Our experimental results using GCC and the SPEC CPU benchmarks show that the automatic construction of optimization levels is feasible in practice, and in addition, yields better optimization levels than GCC's manually derived (-0s, -01, -02 and -03) optimization levels, as well as the optimization levels obtained through random sampling. We also demonstrate that COLE can be used to gain insight into the effectiveness of compiler optimizations as well as to better understand a benchmark's sensitivity to compiler optimizations.

关键词： compiler optimization multi-objective search

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Data routing: A paradigm for efficient data-path synthesis and code generation

Data routing: A paradigm for efficient data-path synthesis a...

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Proceedings of the 7th international symposium on High-Level Synthesis

作者： Lanneer, Dirk Cornero, Marco Goossens, Gert De Man, Hugo IMEC Leuven Belgium

ISBN: (纸本)0818657855

this paper describes a new and effective approach to register and interconnect optimization, which is applicable in a dual context: to reduce chip area in high-level synthesis, and to reduce resource load (and thus execution time) in retargetable code generation. the key idea is to carefully optimize the way in which data is transferred between functional units. the impact on high-level synthesis will be demonstrated with a practical design from the area of telecommunications.

关键词： Critical path analysis

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Storage optimization in a Liberalized Energy Market

Storage Optimization in a Liberalized Energy Market

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7th international symposium on Applied Machine Intelligence and Informatics

作者： Kadar, Peter Budapest Tech Dept Power Syst H-1034 Budapest Hungary

ISBN: (纸本)9781424438013

the energy crisis requires more generation capability, and that is why the importance of the storage technologies increases. In the liberalized energy market the energy storage activity, this way of the "energy speculation" is welcome. In this paper a small scale buy-sale optimization strategy is investigated. In the Budapest Tech a model has been built in the renewable energy park. the strategy could be realized in practice by our small scale pumped storage hydro plant, Fuel cell, wind turbine and PV system.

关键词： energy storage business optimization pumped storage PV wind turbine fuel cell

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