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Proceedings of the 7th international symposium on High-Level Synthesis

作者： Leupers, Rainer Schenk, Wolfgang Marwedel, Peter Univ of Dortmund Dortmund Germany

ISBN: (纸本)0818657855

In a hardware/software codesign environment compilers are needed that map software components of a partitioned system behavioral description onto a programmable processor. Since the processor structure is not static, but can repeatedly change during the design process, the compiler should be retargetable in order to avoid manual compiler adaption for each alternative architecture. A restriction of existing retargetable compilers is that they only generate microcode for the target architecture instead of machine-level code. In this paper we introduce a bootstrapping technique permitting to translate high-level language (HLL) programs into real machine-level code using a retargetable microcode compiler. Retargetability is preserved, permitting to compare different architectural alternatives in a codesign framework within relatively short time.

关键词： Program compilers

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Proceedings - 2012 7th international Conference on P2P, Parallel, Grid, Cloud and Internet Computing, 3PGCIC 2012

Proceedings - 2012 7th International Conference on P2P, Para...

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2012 7th international Conference on P2P, Parallel, Grid, Cloud and Internet Computing, 3PGCIC 2012

the proceedings contain 58 papers. the topics discussed include: load balancing optimization using the algorithm DEPRO in a distributed environment;modeling resource prices in grid markets;MIP model scheduling for BSP parallel applications on multi-cluster environments;analysis of the BitTorrent protocol modified with fountain code;data replication in P2P collaborative systems;large-scale mining of co-occurrences: challenges and solutions;implementing hadoop platform on eucalyptus cloud infrastructure;a data reception method to reduce interruption time for model and motion separated data in P2P streaming environments;distributed systems in the wild: the theoretical foundations and experimental perspectives;parallel perspectives: reverse engineering for generation multi-X;parallel enhanced hybrid evolutionary algorithm for continuous function optimization;and analysis of the BitTorrent protocol modified with multicast.

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An algorithm for automated generation of invariants for loops with conditionals

An algorithm for automated generation of invariants for loop...

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7th international symposium on Symbolic and Numeric Algorithms for Scientific Computing, SYNASC 2005

作者： Kovács, Laura Ildikó Jebelean, Tudor Research Institute for Symbolic Computation Johannes Kepler University Linz Austria

ISBN: (纸本)0769524532

We present an algorithm that generates automatically (algebraic) invariant properties of a loop with conditionals. In the proposed algorithm program analysis is performed in order to transform the code into a form for which algebraic and combinatorial techniques can be applied to obtain invariant properties. these invariants are then used for verifying partial correctness of imperative programs in the theorema system (***). the application of the method is demonstrated in few examples. © 2005 IEEE.

关键词： Invariance

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A Parallelizing Matlab Compiler Framework and Run time for Heterogeneous Systems 17

A Parallelizing Matlab Compiler Framework and Run time for H...

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2015 IEEE 17th international Conference on High Performance Computing and Communications (HPCC)

作者： Skalicky, Sam Lopez, Sonia Lukowiak, Marcin Schmidt, Andrew G. Rochester Inst Technol Dept Comp Engn Rochester NY 14623 USA Univ Southern Calif Inst Informat Sci Los Angeles CA 90089 USA

ISBN: (纸本)9781479989379

Compute-intensive applications incorporate ever increasing data processing requirements on hardware systems. Many of these applications have only recently become feasible thanks to the increasing computing power of modern processors. the Matlab language is uniquely situated to support the description of these compute-intensive scientific applications, and consequently has been continuously improved to provide increasing computational support in the form of multithreading for CPUs and utilizing accelerators such as GPUs and FPGAs. Moreover, to take advantage of the computational support in these heterogeneous systems from the problem domain to the computer architecture necessitates a wide breadth of knowledge and understanding. In this work, we present a framework for the development of compute-intensive scientific applications in Matlab using heterogeneous processor systems. We investigate systems containing CPUs, GPUs, and FPGAs. We leverage the capabilities of Matlab and supplement them by automating the mapping, scheduling, and parallel code generation. Our experimental results on a set of benchmarks achieved from 20x to 60x speedups compared to the standard Matlab CPU environment with minimal effort required on the part of the user.

关键词： graphics processing units mathematics computing multi-threading parallel architectures parallelising compilers FPGA GPU Matlab compiler framework Matlab language compute-intensive scientific application computer architecture heterogeneous processor system heterogeneous system multithreading parallel code generation standard Matlab CPU environment Data transfer Field programmable gate arrays Kernel MATLAB Message systems Processor scheduling Scheduling Heterogeneous computing Matlab compiler MATLAB Multithreading Field programmable gate arrays HETEROGENEOUS SYSTEM Computer Architecture Computer based information systems mathematics computing compilers scheduling of multiprocessor code generation data transmission Parallel architectures Graphics Processing Unit central processing units

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DRStencil: Exploiting Data Reuse within Low-order Stencil on GPU 23

DRStencil: Exploiting Data Reuse within Low-order Stencil on...

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23rd IEEE international Conference on High Performance Computing and Communications, 7th IEEE international Conference on Data Science and Systems, 19th IEEE international Conference on Smart City and 7th IEEE international Conference on Dependability in Sensor, Cloud and Big Data Systems and Applications, HPCC-DSS-SmartCity-DependSys 2021

作者： You, Xin Yang, Hailong Jiang, Zhonghui Luan, Zhongzhi Qian, Depei State Key Laboratory of Software Development Environment Beijing100191 China School of Computer Science and Engineering Beihang University Beijing100191 China

ISBN: (纸本)9781665494571

Stencil computation is widely adopted in scientific applications as one of the most significant computation patterns. Although there are various optimizations proposed to accelerate the stencil computation, the low-order stencil still suffers from limited performance on GPU due to its low computation inten-sity. In this paper, we propose the fusion-partition optimization techniques to accelerate the low-order stencil computation and implement an effective code generation framework DRStencil to automatically generate optimized stencil codes with fusion-partition applied. Specifically, we adopt a four-stage optimization workflow such as time-fusion, partition, forward and backward computation. We also propose an auto-tuning method to deter-mine the optimal parameter settings of the generated stencil codes. We evaluate DRStencil with representative low-order stencils on Nvidia P100, V100, and A100 GPUs. Our evaluation results achieve 1.46 x, 1.59 x, and 1.10 x speedup on average for widely used low-order stencils compared to the state-of-the-art implementations on P100, V100, and A100 GPUs, respectively. © 2021 IEEE.

关键词： codes Smart cities Graphics processing units Manuals Parallel processing Computational efficiency optimization

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Modeling and optimization of DNA recombination

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COMPUTERS & CHEMICAL ENGINEERING 2000年第2-7期24卷 693-699页

作者： Moore, GL Maranas, CD Gutshall, KR Brenchley, JE Penn State Univ Dept Chem Engn Fenske Lab 112A University Pk PA 16802 USA Penn State Univ Dept Biochem & Mol Biol University Pk PA 16802 USA

this paper discusses predictive models for quantifying the outcome of DNA recombination employed in directed evolution experiments for the generation of novel enzymes. Specifically, predictive models are outlined for (i) tracking the DNA fragment size distribution after random fragmentation and subsequent assembly into genes of full length and (ii) estimating the fraction of the assembled full length sequences matching a given nucleotide target. Based on these quantitative models, optimization formulations are constructed which are aimed at identifying the optimal recombinatory length and parent sequences for maximizing the assembly of a sought after sequence target. Computational results show that the recombination outcome is a 'complex' function of the recombinatory length and recombined sequences and illustrate the magnitude of improvements that can be realized. (C) 2000 Elsevier Science Ltd. All rights reserved.

关键词： optimization bioinformatics directed evolution DNA recombination

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CBSOFT 2022 - 13th Congresso Brasileiro de Software;Proceedings - 7th Brazilian symposium on Systematic and Automated Software Testing, SAST 2022

CBSOFT 2022 - 13th Congresso Brasileiro de Software;Proceedi...

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7th Brazilian symposium on Systematic and Automated Software Testing, SAST 2022

ISBN: (纸本)9781450397537

the proceedings contain 8 papers. the topics discussed include: evaluating the effectiveness of regression test suites for extract method validation;a survey of requirements engineering and software testing practices in agile teams;fully-tested code generation from TLA+ specifications;a strategy to support the infeasible test requirements identification;data flow subsumption and its impact on spectrum-based fault localization;an empirical analysis of two mutation testing tools for Java;mutation operators for Java streams;and evaluating a conceptual framework for supporting technical debt management in testing activities – a feasibility study.

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code generation for a DSP processor

Code generation for a DSP processor

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Proceedings of the 7th international symposium on High-Level Synthesis

作者： Cheng, Wei-Kai Lin, Youn-Long Tsing Hua Univ Hsin-Chu Taiwan

ISBN: (纸本)0818657855

We propose a method for compiling an application program into microcodes of a programmable DSP processor. Since most state-of-the-art DSP processors feature some sort of parallel processing architectures, the code generation is a non-trivial task. Based on several scheduling and allocation techniques previously developed by the CAD community for high-level synthesis, we propose a DSP code generator. We emphasize on reducing the memory access and register usage conflicts, which often lengthen the total execution time. Starting with an as soon as possible scheduling without regarding to the resource constraints, we transform the scheduling step-by-step into a legal one. In the mean time, registers are allocated and re-allocated for variables taking into account both the memory access and register usage constraints. A software system called thEDA. DSPCG has been implemented and tested using a set of benchmark programs. Simulation of the generated codes targeted towards the TI TMS320C40 DSP processor shows that the proposed approach is indeed very effective.

关键词： Program processors

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7th international Workshop on Software and Compilers for Embedded Systems, SCOPES 2003

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7th international Workshop on Software and Compilers for Embedded Systems, SCOPES 2003

ISBN: (纸本)3540201459

the proceedings contain 27 papers. the special focus in this conference is on code Size Reduction and code Selection. the topics include: Limited address range architecture for reducing code size in embedded processors;predicated instructions for code compaction;code generation for a dual instruction set processor based on selective code transformation;code instruction selection based on SSA-graphs;a code selection method for SIMD processors with pack instructions;reconstructing control flow from predicated assembly code;control flow analysis for recursion removal;an unfolding-based loop optimization technique;tailoring software pipelining for effective exploitation of zero overhead loop buffer;case studies on automatic extraction of target-specific architectural parameters in complex code generation;extraction of efficient instruction schedulers from cycle-true processor models;a framework for the design and validation of efficient fail-safe fault-tolerant programs;a case study on a component-based system and its configuration;composable code generation for model-based development;retargetable graph-coloring register allocation for irregular architectures;fine-grain register allocation based on a global spill costs analysis;unified instruction reordering and algebraic transformations for minimum cost offset assignment;improving offset assignment through simultaneous variable coalescing;transformation of meta-information by abstract co-interpretation;towards superinstructions for java interpreters;data partitioning for DSP software synthesis;efficient variable allocation for dual memory banks of DSPs;cache behavior modeling of codes with data-dependent conditionals and a fast instruction cache optimizer.

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Memetic differential evolution based on mind evolution algorithm 7

Memetic differential evolution based on mind evolution algor...

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7th international symposium on Computational Intelligence and Industrial Applications, ISCIIA 2016

作者： Zhang, Chunmei Fan, Bingyao Guo, Hongge Gao, Yang Taiyuan University of Science and Technology 66 Waliu Road Wanbailin District TaiyuanShanxi China

ISBN: (纸本)9784990534349

A memetic algorithm combining differential evolution(DE) with mind evolution algorithm(MEA) is proposed in order to achieve a better tradeoff between exploration and exploitation. the initial population is divided into the temporary subpopulations and superior subpopulations by adopting the idea of MEA. then, the differential mutant and crossover operators of DE are used to improve the performance of the individuals. Furthermore, the similartax and dissimilation operators are adopted to update the individuals for next generation. the performance of the proposed memetic algorithm is shown by comparing with the basic DE and MEA respectively. the numerical results show that the proposed algorithm has excellent performance in terms of solution quality and convergence speed for all test problems given in this study. © 2016, Fuji Technology Press. All rights reserved.

关键词： optimization

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