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检索条件"任意字段=7th International Symposium on Parallel and Distributed Computing"

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parallel implementation of Strassen's matrix multiplication algorithm for heterogeneous clusters

Parallel implementation of Strassen's matrix multiplication ...

引用

international symposium on parallel and distributed Processing (IPDPS)

作者： Y. Ohtaki D. Takahashi T. Boku M. Sato Masters program in Science and Engineering University of Tsukuba Japan Institute of Information Sciences and Electronics University of Tsukuba Japan

Summary form only given. We propose a new distribution scheme for a parallel Strassen's matrix multiplication algorithm on heterogeneous clusters. In the heterogeneous clustering environment, appropriate data distribution is the most important factor for achieving maximum overall performance. However, Strassen's algorithm reduces the total operation count to about 7/8 times per one recursion and, hence, the recursion level has an effect on the total operation count. thus, we need to consider not only load balancing but also the recursion level in Strassen's algorithm. Our scheme achieves both load balancing and reduction of the total operation count. As a result, we achieve a speedup of nearly 21.7% compared to the conventional parallel Strassen's algorithm in a heterogeneous clustering environment.

关键词： Clustering algorithms Load management Hardware Concurrent computing Computer networks Costs Scalability parallel processing Supercomputers Libraries

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High performance hierarchical torus network under matrix transpose traffic patterns

High performance hierarchical torus network under matrix tra...

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international symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： M.M.H. Rahman S. Horiguchi Graduate School of Information Science Japan Advanced Institute of Science and Technology Japan Graduate School of Information Science University of Tohoku Japan

Interconnection networks play a crucial role in the performance of massively parallel computers. Hierarchical interconnection networks provide high performance at low cost by exploring the locality that exists in the communication patterns of massively parallel computers. A hierarchical torus network (HTN) is a 2D-torus network of multiple basic modules, in which the basic modules are 3D-torus networks that are hierarchically interconnected for higher level networks. the static network performance of the HTN has already been studied and has been shown to be good. Dynamic communication performance has been evaluated under uniform traffic patterns but not under a nonuniform traffic, such as matrix transpose traffic patterns. In this paper, we present a deadlock-free routing algorithm for the HTN using 3 virtual channels and evaluate the network's dynamic communication performance under matrix transpose traffic, using the proposed routing algorithm. We evaluate the dynamic communication performance of HTN, H3D-mesh, TESH, and mesh networks by computer simulation. We find that the dynamic communication performance of HTN is better than that of the H3D-mesh, TESH, and mesh networks.

关键词： Telecommunication traffic Multiprocessor interconnection networks Computer networks Concurrent computing Traffic control Routing Mesh networks Costs High performance computing System recovery

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Peer-to-peer cooperative caching in a hybrid data delivery environment

Peer-to-peer cooperative caching in a hybrid data delivery e...

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international symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： Chi-Yin Chow Hong Va Leong A. Chan Department of Computing Hong Kong Polytechnic University Hong Kong China

In a conventional mobile environment, mobile clients retrieve data items from database servers via mobile support stations, by downloading the items over scalable broadcast channels (push-based), requesting them over shared point-to-point channels (pull-based), or making use of both types of channels to retrieve them (hybrid). Caching is a key technique for improving data retrieval performance of mobile clients, regardless of the data delivery mechanism. the emergence of robust peer-to-peer technologies now brings to reality what we call "cooperative caching" in which mobile clients can access data items from the cache in their neighboring peers, thereby adding a new dimension for data caching. this paper studies the system performance of a cooperative caching scheme, called COCA, in a hybrid data delivery environment, and proposes a cooperative cache replacement scheme, called CORE, for mobile systems. the performance of COCA and CORE schemes is evaluated through a number of simulated experiments. the experiment results show that COCA effectively improves the system performance in push-based and hybrid-data delivery environments, especially in a heavily-loaded environment. the results also indicate that CORE can further improve on the access latency and reduce the number of expensive server requests, which consume scarce pull-based bandwidth.

关键词： Peer to peer computing Cooperative caching Information retrieval Mobile computing System performance Network servers Bandwidth Mobile communication Databases Broadcasting

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A network security architectural approach for systems integrity using multi agent systems engineering

A network security architectural approach for systems integr...

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international symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： G.A.S. Torrellas

Ideally, information systems security enables management to have confidence that their computational systems provide the information requested and expected, while denying accessibility to those who have no right to it. the analysis of incidents resulting in damage to information systems show that most losses were still due to errors or omissions by authorized users, actions of disgruntled employees, and an increase in external penetrations of systems by outsiders. Traditional controls are normally inadequate in these cases or are focused on the wrong threat, resulting in the exposure of vulnerability. Security is a critical parameter for the expansion and wide usage of agent technology. A threat model is constructed and subsequently the basic techniques to deal effectively with these threats are analyzed. this paper presents a dynamic, extensible, configurable and interoperable security architecture for mobile agent systems. It is explained how this architecture can be used to tackle a big part of security threats. All the components of the security architecture are analyzed while we also argue for the benefits they offer.

关键词： Systems engineering and theory Information security Data security Costs Control systems Resource management Risk management Protection Information resources distributed processing

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Bounds on the client-server incremental computing

Bounds on the client-server incremental computing

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international symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： Cho-chin Lin Tsan-sheng Hsu Da-wei Wang Department of Electronic Engineering National I-Lan University Yilan Taiwan Institute of Information Science Academia Sinica Taipei Taiwan

ISBN: (纸本)0769521355

We discuss the problem of finding a dominating sequence for sending the input data items from a low-end client to a server for computational intensive tasks under the realistic assumption of unpredictable communication behaviors. Under the assumption, the client sends the input data items using a specified sequence to maximum the number of computations performed at the server at any moment. the sequence-finding problem is NP-hard for the general case. In this paper, we address two fundamental and useful applications: matrix multiplication and fast Fourier transform. We have shown that the sequence-finding problems of the applications can be solved optimally in linear time. However, we have also shown counter examples to rule out any possibility of finding a dominating sequence for the sparse cases. Finally, a simulation is conducted to show the correctness and usefulness of our results.

关键词： Signal processing algorithms Computer networks Information science Sparse matrices Fast Fourier transforms Computational modeling Network servers Hardware Discrete Fourier transforms Delay

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Performance of parallel logic event simulation on PC-cluster

Performance of parallel logic event simulation on PC-cluster

引用

international symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： T.T. Le J. Rejeb Department of Electrical Engineering San Jose State University Foundation San Jose CA USA

PC-cluster is becoming more and more popular in many scientific and engineering applications, but not in electronic design areas. One of the reasons that parallel simulations have not been popularized is due to the high cost of frequent communications of small messages. Several simulation techniques have been aggressively studied and developed in the past ten years. these studies mostly focused on parallel VHDL simulation. In this paper, we show the effects of PC-cluster communication latencies on the performance of parallel discrete event simulation. We performed the experiments with two equivalent 8-node PC-cluster systems, one with regular Ethernet cards and one with Myrinet network cards. In order to study the effects of communication costs on the overall performance of parallel simulation algorithms, our study concentrates on fundamental techniques of discrete parallel event simulation scheme. the simulation processes are synchronized by the time warp mechanism and the problem domain is partitioned for best parallel performance. the speedup results show that although current PC-cluster technology is ready for parallel logic simulator, even for high-demanding communication applications, new algorithms that can avoid or minimize the computational rolling-back must be developed in order to catch up the rapid advancement of microprocessor technologies.

关键词： Logic Discrete event simulation Computational modeling Costs Partitioning algorithms Design engineering Delay Ethernet networks Time warp simulation Concurrent computing

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IDR: an intrusion detection router for defending against distributed denial-of-service (DDoS) attacks

IDR: an intrusion detection router for defending against dis...

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international symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： E.Y.K. Chan H.W. Chan K.M. Chan V.P.S. Chan S.T. Chanson M.M.H. Cheung C.F. Chong K.P. Chow A.K.T. Hui L.C.K. Hui L.C.K. Lam W.C. Lau K.K.H. Pun A.Y.F. Tsang W.W. Tsang S.C.W. Tso Dit-Yan Yeung K.Y. Yu Department of Computer Science and Information Systems University of Hong Kong Hong Kong China Department of Computer Science and Information Systems Hong Kong University of Science and Technology Hong Kong China

distributed denial-of-service (DDoS) attack has turned into one of the major security threats in recent years. Usually the only solution is to stop the services or shut down the victim and then discard the attack traffic only after the DDoS attack characteristics (such as the destination ports of the attack packets) are known. In this paper, we introduce a generic DDoS attack detection mechanism as well as the design and setup of a testbed for performing experiments and analysis. Our results showed that the mechanism can detect DDoS attack. this enables us to proceed to the next steps of packet classification and traffic control.

关键词： Intrusion detection Computer crime Testing Performance evaluation Performance analysis Traffic control Computer science Protection Filters Large-scale systems

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Implementing sequentially consistent programs on processor consistent platforms

Implementing sequentially consistent programs on processor c...

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international symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： L. Higham J. Kawash Department of Computer Science University of Calgary Calgary Canada Department of Computer Science American University of Sharjah Sharjah UAE

this paper investigates the existence of compilers to convert programs that use shared read/write variables, with sequentially consistent memory semantics, to programs that use read/write variables with the semantics of one variant of processor consistency, known as PC-G. We first provide a simple program transformation, and prove that it compiles any 2-process program with only single-writer variables. We show that this transformation is not a general compiler for 3 or more processes; however, it does correctly transform some specific n-process programs. In particular, for the special case of the (expected) wait-free Test&Set algorithm of Tromp and Vitanyi, our transformation extends to any number of processes. thus, one notable outcome is an implementation of Test&Set on PC-G that uses only reads and writes of shared variables. this is the first expected wait-free implementation of Test&Set on any weak memory model, and illustrates the use of randomization with a weak memory model.

关键词： Testing Algorithm design and analysis Computer science Program processors Read-write memory Hardware distributed algorithms Scalability Availability Power system modeling

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Identifying transcriptional regulatory sites in the human genome using an integrated computation

Identifying transcriptional regulatory sites in the human ge...

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international symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： Hsien-Da Huang Jorng-Tzong Horng Yi-Ming Sun Ann-Ping Tsou Shir-Ly Huang Department of Biological Science and Technology Institute of Bioinformatics National Chiao Tung University Hsinchu Taiwan Department of Computer Science and Information Engineering National Central University Chungli Taiwan Institute of Biotechnology in Medicine National Yang-Ming University Taipei Taiwan Department of Life Science National Central University Chungli Taiwan

ISBN: (纸本)0769521355

Recently, biological databases and analytical methods have become available for analyzing gene expression and transcriptional regulatory sequences. However, users must make the complicated analyses to query the data in various databases, and to analyze the gene upstreams using various predictive tools. Beyond methods for predicting transcriptional regulatory sites, new automated and integrated methods for analyzing gene upstream sequences on a higher level are urgently required. We present an integrated system to predict transcriptional regulatory sites and detect co-occurrence of these regulatory sites after a set of genes are input. the system comprises a biological data warehousing system, pattern discovery programs, pattern occurrence association detectors and user interfaces. User profiles and history pages enable users to trace the sequence analyses for transcriptional regulatory sites.

关键词： Humans Genomics Bioinformatics Databases Data analysis Biology computing Gene expression Warehousing Detectors User interfaces

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Dynamic update of shortest path tree in OSPF

Dynamic update of shortest path tree in OSPF

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international symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： Bin Xiao Jiannong Cao Qingfeng Zhuge Zili Shao E.H.M. Sha Department of Computing Hong Kong Polytechnic University Hong Kong China Department of Computer Science University of Texas Dallas Richardson TX USA

the shortest path tree (SPT) construction is a critical issue to the high performance routing in an interior network using link state protocols, such as open shortest path first (OSPF) and IS-IS. In this paper, we propose a new efficient algorithm for dynamic SPT update to avoid the disadvantages (e.g. redundant computation) caused by static SPT update algorithms. the new algorithm is based on the understanding of the update procedure to reduce redundancy. Only significant elements that contribute to the construction of new SPT from the old one are focused on. the efficiency of our algorithm is improved because it only pay attention to the edges really count for the update process. the running time for the proposed algorithm is maximum reduced, which is shown through experimental results. Furthermore, our algorithm can be easily generalized to solve the SPT updating problem in a graph with negative weight edges and applied to the scenario of multiple edge weight changes.

关键词： Routing protocols Heuristic algorithms Computer networks Network topology Computer science IP networks Costs Delay Buildings Telecommunication traffic

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