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14th acm sigplan symposium on principles and practice of parallel Programming

作者： Scott, Stephen L. Engelmann, Christian Vallee, Geoffroy R. Naughton, thomas Tikotekar, Anand Ostrouchov, George Leangsuksun, Chokchai (Box) Naksinehaboon, Nichamon Nassar, Raja Paun, Mihaela Mueller, Frank Wang, Chao Nagarajan, Arun B. Varma, Jyothish Oak Ridge Natl Lab Oak Ridge TN 37831 USA Louisiana Tech Univ Ruston LA 71270 USA N Carolina State Univ Raleigh NC 27695 USA

ISBN: (纸本)9781605583976

In order to address anticipated high failure rates, resiliency characteristics have become an urgent priority for next-generation extreme-scale high-performance computing (HPC) systems. this poster describes our past and ongoing efforts in novel fault resilience technologies for HPC. Presented work includes proactive fault resilience techniques, system and application reliability models and analyses, failure prediction, transparent process- and virtual-machine-level migration, and trade-off models for combining preemptive migration with checkpoint/restart. this poster summarizes our work and puts all individual technologies into context with a proposed holistic fault resilience framework.

关键词： Design Measurement Performance Reliability

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POSTER: Hardening Selective Protection across Multiple Program Inputs for HPC Applications 27

POSTER: Hardening Selective Protection across Multiple Progr...

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27th acm sigplan symposium on principles and practice of parallel Programming (PPoPP)

作者： Huang, Yafan Guo, Shengjian Di, Sheng Li, Guanpeng Cappello, Franck Univ Iowa Iowa City Iowa IA USA Baidu Secur Sunnyvale CA USA Argonne Natl Lab Lemont Lemont IL USA

ISBN: (纸本)9781450392044

With the ever-shrinking size of transistors and increasing scale of applications, silent data corruptions (SDCs) have become a common yet serious issue in HPC applications. Selective instruction duplication (SID) is a popular fault-tolerance technique that can obtain a high SDC coverage with low-performance overhead, as it selects the most vulnerable parts of a program for protection with priority. However, existing studies of SID are confined to single program input in the evaluation, assuming that the error resilience of the program remains similar across inputs, leading to a drastic loss of SDC coverage from SID when the protected program runs different inputs. Hence, we proposed Sentinel, an automated compiler-based framework to mitigate the loss of SDC coverage. Evaluation results show that Sentinel can effectively mitigate the loss of SDC coverage (up to 97.00%) across multiple inputs, which significantly hardens existing SID techniques.

关键词： Error Resilience Fault Injection Compiler High Performance computing

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Scalable Top-K Retrieval with Sparta 20

Scalable Top-K Retrieval with Sparta

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25th acm sigplan symposium on principles and practice of parallel Programming (PPoPP)

作者： Sheffi, Gali Basin, Dmitry Bortnikov, Edward Carmel, David Keidar, Idit Technion Haifa Israel Yahoo Res Haifa Israel Amazon Haifa Israel

ISBN: (纸本)9781450368186

Many big data processing applications rely on a top-k retrieval building block, which selects (or approximates) the k highest-scoring data items based on an aggregation of features. In web search, for instance, a document's score is the sum of its scores for all query terms. Top-k retrieval is often used to sift through massive data and identify a smaller subset of it for further analysis. Because it filters out the bulk of the data, it often constitutes the main performance bottleneck. Beyond the rise in data sizes, today's data processing scenarios also increase the number of features contributing to the overall score. In web search, for example, verbose queries are becoming mainstream, while state-of-the-art algorithms fail to process long queries in real-time. We present Sparta, a practical parallel algorithm that exploits multi-core hardware for fast (approximate) top-k retrieval. thanks to lightweight coordination and judicious context sharing among threads, Sparta scales both in the number of features and in the searched index size. In our web search case study on 50M documents, Sparta processes 12-term queries more than twice as fast as the state-of-the-art. On a tenfold bigger index, Sparta processes queries at the same speed, whereas the average latency of existing algorithms soars to be an order-of-magnitude larger than Sparta's.

关键词： parallel computing multi-threading performance information retrieval web search top-k search

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POSTER: Remote OpenMP Offloading 27

POSTER: Remote OpenMP Offloading

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27th acm sigplan symposium on principles and practice of parallel Programming (PPoPP)

作者： Patel, Atmn Doerfert, Johannes Univ Waterloo Waterloo Waterloo ON Canada Argonne Natl Lab Lemont Lemont IL USA

ISBN: (纸本)9781450392044

OpenMP has a long and successful history in parallel programming for CPUs, and more recently GPUs through accelerator offloading. In this work we show that the OpenMP accelerator offloading model is sufficient to seamlessly and efficiently utilize more than a single compute node, and its connected accelerators, without source code or compiler modifications. For applications that support multi-device offloading, any combination of local and remote CPUs and accelerators can be utilized simultaneously, fully transparent to the user. Our low-overhead implementation of Remote OpenMP Offloading is publicly available in the LLVM/OpenMP compiler infrastructure with LLVM 12 and later. To evaluate our work we provide detailed studies on micro benchmarks, as well as scaling results for two HPC proxy applications. We show perfect (weak) scaling across dozens of GPUs in multiple hosts with effectiveness that is directly proportional to the ratio of computation versus memory transfer time. Our work outlines the capabilities and limits of OpenMP 5.1 to efficiently utilize a distributed heterogeneous system without source, compiler, or language modifications.

关键词： OpenMP GPGPU distributed computing

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Mapping parallelism to Multi-cores: A Machine Learning Based Approach

Mapping Parallelism to Multi-cores: A Machine Learning Based...

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14th acm sigplan symposium on principles and practice of parallel Programming

作者： Wang, Zheng O'Boyle, Michael F. P. Univ Edinburgh Sch Informat Edinburgh EH8 9YL Midlothian Scotland

ISBN: (纸本)9781605583976

the efficient mapping of program parallelism to multi-core processors is highly dependent on the underlying architecture. this paper proposes a portable and automatic compiler-based approach to mapping such parallelism using machine learning. It develops two predictors: a data sensitive and a data insensitive predictor to select the best mapping for parallel programs. they predict the number of threads and the scheduling policy for any given program using a model learnt off-line. By using low-cost profiling runs, they predict the mapping for a new unseen program across multiple input data sets. We evaluate our approach by selecting parallelism mapping configurations for OpenMP programs on two representative but different multi-core platforms (the Intel Xeon and the Cell processors). Performance of our technique is stable across programs and architectures. On average, it delivers above 96% performance of the maximum available on both platforms. It achieve, on average, a 37% (up to 17.5 times) performance improvement over the OpenMP runtime default scheme on the Cell platform. Compared to two recent prediction models, our predictors achieve better performance with a significant lower profiling cost.

关键词： Experimentation Languages Performance Compiler optimization Performance modeling Machine learning Artificial neural networks Support vector machine

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Andorra-I: A parallel prolog system that transparently exploits both and-and or-parallelism 91

Andorra-I: A parallel prolog system that transparently explo...

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3rd acm sigplan symposium on principles and practice of parallel Programming, PPOPP 1991

作者： Costa, Vitor Santos Warren, David H. D. Yang, Rong Department of Computer Science University of Bristol BristolBS8 ITR United Kingdom

ISBN: (纸本)0897913906

Andorra-I is an experimental parallel Prolog system that transparently exploits both dependent and-parallelism and or-parallelism. It constitutes the first implementation of the Basic Andorra model, a parallel execution model for logic programs in which determinate goals are executed before other goals. this model, besides combining two of the most important forms of implicit parallelism in logic programs, also provides a form of implicit coroutining. this means that Andorra-I not only supports standard Prolog but also provides the capabilities of flat committed-choice languages such as Parlog and GHC. © 1991 Association for computing Machinery. All Rights Reserved.

关键词： Computer circuits

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computing constructor forms with non terminating rewrite programs 06

Computing constructor forms with non terminating rewrite pro...

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PPDP'06 - 8th acm sigplan symposium on principles and practice of Declarative Programming

作者： Gnaedig, Isabelle Kirchner, Hélène LORIA-INRIA 615 rue du Jardin Botanique F-54602 Villers-les-Nancy Cedex France LORIA-CNRS Campus Scientifique BP 239 F-54506 Vandoeuvre-les-Nancy Cedex France

ISBN: (纸本)1595933883

In the context of the study of rule-based programming, we focus in this paper on the property of C-reducibility, expressing that every term reduces to a constructor term on at least one of its rewriting derivations. this property implies completeness of function definitions, and enables to stop evaluations of a program on a constructor form, even if the program is not terminating. We propose an inductive procedure proving C-reducibility of rewriting. the rewriting relation on ground terms is simulated through an abstraction mechanism and narrowing. the induction hypothesis allows assuming that terms smaller than the starting terms rewrite into a constructor term. the existence of the induction ordering is checked during the proof process, by ensuring satisfiability of ordering constraints. the proof is constructive, in the sense that the branch leading to a constructor term can be computed from the proof trees establishing C-reducibility for every term. Copyright © 2006 acm.

关键词： Logic programming

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Using generative design patterns to generate parallel code for a distributed memory environment 03

Using generative design patterns to generate parallel code f...

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9th acm sigplan symposium on principles and practice of parallel Programming

作者： Tan, K Szafron, D Schaeffer, J Anvik, J MacDonald, S Univ Alberta Dept Comp Sci Edmonton AB T6G 2E8 Canada Univ Waterloo Sch Comp Sci Waterloo ON N2L 3G1 Canada

ISBN: (纸本)9781581135886

A design pattern is a mechanism for encapsulating the knowledge of experienced designers into a re-usable artifact. parallel design patterns reflect commonly occurring parallel communication and synchronization structures. Our tools, CO2P3S (Correct Object-Oriented Pattern-based parallel Programming System) and MetaCO(2)P(3)S, use generative design patterns. A programmer selects the parallel design patterns that are appropriate for an application, and then adapts the patterns for that specific application by selecting from a small set of code-configuration options. CO2P3S then generates a custom framework for the application that includes all of the structural code necessary for the application to ran in parallel. the programmer is only required to write simple code that launches the application and to fill in some application-specific sequential hook routines. We use generative design patterns to take an application specification (parallel design patterns + sequential user code) and use it to generate parallel application code that achieves good performance in shared memory and distributed memory environments. Although our implementations are for Java, the approach we describe is tool and language independent. this paper describes generalizing CO2P3S to generate distributed-memory parallel solutions.

关键词： performance design reliability languages parallel programming design patterns frameworks programming tools

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Scaling LAPACK Panel Operations Using parallel Cache Assignment

Scaling LAPACK Panel Operations Using Parallel Cache Assignm...

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15th acm sigplan symposium on principles and practice of parallel Programming

作者： Castaldo, Anthony M. Whaley, R. Clint Univ Texas San Antonio Dept Comp Sci San Antonio TX 78249 USA

ISBN: (纸本)9781605587080

In LAPACK many matrix operations are cast as block algorithms which iteratively process a panel using an unblocked algorithm and then update a remainder matrix using the high performance Level 3 BLAS. the Level 3 BLAS have excellent weak scaling, but panel processing tends to be bus bound, and thus scales with bus speed rather than the number of processors (p). Amdahl's law therefore ensures that as p grows, the panel computation will become the dominant cost of these LAPACK routines. Our contribution is a novel parallel cache assignment approach which we show scales well with p. We apply this general approach to the QR and LU panel factorizations on two commodity 8-core platforms with very different cache structures, and demonstrate superlinear panel factorization speedups on both machines. Other approaches to this problem demand complicated reformulations of the computational approach, new kernels to be tuned, new mathematics, an inflation of the high-order flop count, and do not perform as well. By demonstrating a straight-forward alternative that avoids all of these contortions and scales with p, we address a critical stumbling block for dense linear algebra in the age of massive parallelism.

关键词： ATLAS LAPACK QR LU factorization parallel multicore multi-core GPU

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parallel 'go with the winners' algorithms in distributed memory models

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JOURNAL OF parallel AND DISTRIBUTED computing 2003年第9期63卷 801-814页

作者： Peinado, M Lengauer, T Microsoft Corp Redmond WA 98052 USA Max Planck Inst Comp Sci D-66123 Saarbrucken Germany

We parallelize the 'go with the winners' algorithm of Aldous and Vazirani (in: Proceedings of the 35th IEEE symposium on the Foundations of Computer Science, IEEE Computer Society Press, Silver Spring., MD, 1994, pp. 492-501) and analyze the resulting parallel algorithm in the LogP-model (in: Proceedings of the Fourth acm sigplan symposium on principles & practice of parallel Programming, 1993, pp. 1-12). the main issues in the analysis are load imbalances and communication delays. the result of the analysis is a practical algorithm which, under reasonable assumptions, achieves linear speedup. Finally, we analyze our algorithm for a concrete application: generating models of amorphous chemical structures. (C) 2003 Elsevier Inc. All rights reserved.

关键词： parallel algorithms go with the winners LogP model second moment method load balancing amorphous solids self-avoiding walks

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