Evolution is an important sub-area of study in biological science, where given a set of taxa, the goal is to reconstruct their evolutionary history, or phylogeny. One very recent approach is to predict a local phyloge...
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ISBN:
(纸本)3540285385
Evolution is an important sub-area of study in biological science, where given a set of taxa, the goal is to reconstruct their evolutionary history, or phylogeny. One very recent approach is to predict a local phylogeny for every subset of 4 taxa, called a quartet topology, and then to assemble a phylogeny for the whole set of taxa satisfying these predicted quartet topologies. In general, the predicted quartet topologies might not always agree with each other, and thus the objective function becomes to satisfy a maximum number of them. this is the well known Maximum Quartet Consistency (MQC) problem. In the past, the MQC problem has been solved by dynamic programming and the so-called fixed-parameter method. Recently, we have proposed to solve the MQC in answer set programming. In this note, we summarize the theoretical results of this approach and report new experimental results for the purpose of comparison, which show that our approach in answer set programming is favored over the existing approaches based on dynamic programming and fixed-parameter method. In particular, some of the hard instances (where the error ratio is high) that were not reported to be solved in other approaches can now be solved in our approach.
Learning rules with exceptions may be of interest, especially if the exceptions are not important in some sense. Standard Inductive logicprogramming (ILP) algorithms and classical first order logic are not well-suite...
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ISBN:
(纸本)3540273263
Learning rules with exceptions may be of interest, especially if the exceptions are not important in some sense. Standard Inductive logicprogramming (ILP) algorithms and classical first order logic are not well-suited for managing rules with exceptions. Indeed, a hypothesis that is induced accumulates all the exceptions of the rules contained in it. Moreover, with multiple-class problems, classifying an example in two different classes (even if one is the right one) is not correct, so a rule that contains some exceptions may prevent another rule which has no exception from being useful. this paper proposes a new possibilistic logic framework for weighted ILP. It induces rules which are progressively more and more accurate, and allows us to manage exceptions by controlling their accumulation. In this setting, we first propose an algorithm for learning rules when the background knowledge and the examples are stratified into layers having different levels of priority or certainty. this allows the induction of general but uncertain rules together with more specific and less uncertain rules. A second algorithm is presented, which does not require an initial weighted database, but still learn a default set of rules in the possibilistic setting.
Multidimensional dynamic logic programs are a paradigm which allows to express (partially) hierarchically ordered evolving knowledge bases through (partially) ordered multi sets of logic programs and allowing to solve...
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ISBN:
(纸本)3540285385
Multidimensional dynamic logic programs are a paradigm which allows to express (partially) hierarchically ordered evolving knowledge bases through (partially) ordered multi sets of logic programs and allowing to solve contradictions among rules in different programs by allowing rules in more important programs to reject rules in less important ones. this class of programs extends the class of dynamic logic program that provides meaning and semantics to sequences of logic programs. Recently a semantics named refined stable model semantics has fixed some counterintuitive behaviour of previously existing semantics for dynamic logic programs. However, it is not possible to directly extend the definitions and concepts of the refined semantics to the multidimensional case and hence more sophisticated principles and techniques are in order. In this paper we face the problem of defining a proper semantics for multidimensional dynamic logic programs by extending the idea of well supported model to this class of programs and by showing that this concept alone is enough for univocally characterizing a proper semantics. We then show how the newly defined semantics coincides withthe refined one when applied to sequences of programs.
the proceedings contain 76 papers. the topics discussed include: multi-media applications and imprecise computation;wireless sensor systems - Constraints and opportunities;BIST technique for GALS systems;functional ve...
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ISBN:
(纸本)0769524338
the proceedings contain 76 papers. the topics discussed include: multi-media applications and imprecise computation;wireless sensor systems - Constraints and opportunities;BIST technique for GALS systems;functional vectors generation for RT-Level verilog descriptions based on path enumeration and constraint logicprogramming;power-composition profile driven Co-synthesis with power management selection for dynamic and leakage energy reduction;a low-power FIR filter using combined residue and radix-2 signed-digit representation;approximating trigonometric functions withthe laws of sines and cosines using the logarithmic number system;characterization of wavelet-based image coding systems for algorithmic fault detection;improved fault emulation for synchronous sequential circuits;and defect-oriented test- and layout-generation for standard-cell ASIC designs.
Two approaches to logicprogramming with probabilities emerged over time: bayesian reasoning and probabilistic satisfiability (PSAT). the attractiveness of the former is in tying the logicprogramming research to the ...
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this paper proposes a method for detecting misclassifications of a classification rule and then revising them. Given a rule and a set of examples, the method divides misclassifications by the rule into miscovered exam...
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We present how common J(AVA) C-ARD security properties can be formalised in Dynamic logic and verified, mostly automatically, withthe KeY system. the properties we consider, are a large subset of properties that are ...
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ISBN:
(纸本)354025420X
We present how common J(AVA) C-ARD security properties can be formalised in Dynamic logic and verified, mostly automatically, withthe KeY system. the properties we consider, are a large subset of properties that are of importance to the smart card industry. We discuss the properties one by one, illustrate them with examples of real-life, industrial size, J(AVA) C-ARD applications, and show how the properties are verified withthe KeY Prover - an interactive theorem prover for J(AVA) C-ARD source code based on a version of Dynamic logicthat models the full J(AVA) C-ARD standard. We report on the experience related to formal verification Of J(AVA) C-ARD programs we gained during the course of this work. thereafter, we present the current state of the art of formal verification techniques offered by the KeY system and give an assessment of interactive theorem proving as an alternative to static analysis.
Possibilistic Defeasible logicprogramming (P-DeLP) is a logicprogramming language which combines features from argumentation theory and logicprogramming, incorporating as well the treatment of possibilistic uncerta...
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In this paper we explore a topic which is at the intersection of two areas of Machine Learning: namely Support Vector Machines (SVMs) and Inductive logicprogramming (ILP). We propose a general method for constructing...
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this paper presents the IP Core design of PLC (Programmable logic Controller) microprocessor that includes a special boolean process unit after analysing PLC programming language, instruction execution characteristics...
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ISBN:
(纸本)0780392922
this paper presents the IP Core design of PLC (Programmable logic Controller) microprocessor that includes a special boolean process unit after analysing PLC programming language, instruction execution characteristics and current PLC disadvantage. the novel microprocessor based on RISC architecture for PLC accords with PLCs international standard and its systematic design requirement. It is successfully synthesized and simulated with EDA tools and implemented in FPGA of Altera's EP20K200EFC484. As a microprocessor IP Core for PLC, its particular design of memory bit access interface unit and Boolean processor unit can greatly improve the real time performance and stability for PLC, its design scheme and experimental result will contribute to further research and development of relevant products.
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