the author presents an alternative architecture for the arithmetic units in pipelined residue-number-system applications. this architecture uses feedback shift logic to implement residue adders and multipliers, togeth...
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ISBN:
(纸本)081861918X
the author presents an alternative architecture for the arithmetic units in pipelined residue-number-system applications. this architecture uses feedback shift logic to implement residue adders and multipliers, together with novel data representations derived from the multiplicative group of finite rings. Each stage can be implemented with only one exclusive-OR delay. thus this architecture shows promise in increasing the throughput of residue arithmetic units over conventional logic and ROM (read-only memory) designs.
the authors describe Honeywell Object-oriented programming System (HOPS), which provides an environment for the development, execution and evaluation of fault-tolerant distributed software. HOPS provides an object-ori...
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ISBN:
(纸本)081861918X
the authors describe Honeywell Object-oriented programming System (HOPS), which provides an environment for the development, execution and evaluation of fault-tolerant distributed software. HOPS provides an object-oriented programming language by extending Modula-2 withthe language constructs required to support fault tolerance and distribution. Distribution is supported through a user-transparent remote-procedure-call facility. Fault tolerance is supported by allowing the specification of fault-tolerance mechanisms and policies on a per-object basis.
the authors develop novel techniques 1) to retrieve efficiently a set of related knowledge using a hierarchical model of sentence meaning, and 2) to handle comprehensively frame-based representation using pattern matc...
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ISBN:
(纸本)081861918X
the authors develop novel techniques 1) to retrieve efficiently a set of related knowledge using a hierarchical model of sentence meaning, and 2) to handle comprehensively frame-based representation using pattern matching in an object-oriented programming language. they discuss several features to cope with maintenance of the knowledge base and unknown words in users' questions. An explanation is presented of LISP-PAL's frame-based knowledge representation, its pattern-matching, and its system evaluation with testers.
the filter concept is broadened to include database integrity constaints. the constraints are viewed as the selection and projection operations which control the data flow between the storage devices and a host system...
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ISBN:
(纸本)081861918X
the filter concept is broadened to include database integrity constaints. the constraints are viewed as the selection and projection operations which control the data flow between the storage devices and a host system. they are formalized in canonical forms. Several filter simplification techniques are described.
A description is given of the unification of the document production cycle. the author introduces documentation tools and techniques useful to enhancing productivity. An incentive system is presented which is intended...
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ISBN:
(纸本)081861918X
A description is given of the unification of the document production cycle. the author introduces documentation tools and techniques useful to enhancing productivity. An incentive system is presented which is intended to reduce development costs. A summary lists several key ways in which this contributes to development environment productivity issues.
the author presents three hardware solutions for solving the generation intersection problem. these solutions can be implemented as an algorithm on parallel computers or special-purpose VLSI circuits can be designed. ...
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ISBN:
(纸本)081861918X
the author presents three hardware solutions for solving the generation intersection problem. these solutions can be implemented as an algorithm on parallel computers or special-purpose VLSI circuits can be designed. Next a solution is presented for sorting nonunique keys in O(log n) time. Finally, the author presents a novel solution for the 3-D containment problem using quad trees.
We present a schematic functional programming language coupled with a logic of programs. Our language allows for μ-recursion, λ-abstraction, nondeterminism and calls to predefined functions. We define a denotational...
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Parallel algorithms for balancing any threaded binary search tree of 2n-1 - 1 n - 1 nodes are developed. A Shared-memory model is used for the proposed algorithm. the number of processors used in the algorithms is red...
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ISBN:
(纸本)081861918X
Parallel algorithms for balancing any threaded binary search tree of 2n-1 - 1 < N ≤ 2n - 1 nodes are developed. A Shared-memory model is used for the proposed algorithm. the number of processors used in the algorithms is reduced from (2n - 1) to the number of nodes in the tree. the developed parallel algorithms have constant time complexity and require O(N) additional space.
the authors propose the concept of concurrent correspondent modules as a strategy to implement software fault tolerance. It is based on the concurrent execution of the primary, and its redundant correspondent versions...
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ISBN:
(纸本)081861918X
the authors propose the concept of concurrent correspondent modules as a strategy to implement software fault tolerance. It is based on the concurrent execution of the primary, and its redundant correspondent versions. Error detection and forward error recovery are performed by the comparative test. Using Ada tasks in conjunction withthe abort facility, concurrent correspondent modules are easily and efficiently implemented. the use of concurrent Ada enhances the power of concurrent correspondent modules, making this an elegant, effective and feasible alternative to other fault-tolerant approaches.
A Pascal compiler system has been developed to run in five phases as a cross-compiler and in native mode to run on an existing multiprocessor system in parallel with approximately even loading of the processors. the p...
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ISBN:
(纸本)081861918X
A Pascal compiler system has been developed to run in five phases as a cross-compiler and in native mode to run on an existing multiprocessor system in parallel with approximately even loading of the processors. the parallel processor system connects six Z8001 processors by a crossbar switch to four memory modules. Each processor owns a private cache memory for instructions for increasing processor and systems performance. Peripheral devices (terminals, drives, VAS-780 interface, etc.) are distributed among the processors, so that no special I/O-processors are needed. the speedup observed reaches a quite acceptable value.
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