A system to insert visual objects into real image sequences in real time is presented. the system consists of off-the-shelf hardware and software. the system uses a region tracking algorithm based on a normalized affi...
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A system to insert visual objects into real image sequences in real time is presented. the system consists of off-the-shelf hardware and software. the system uses a region tracking algorithm based on a normalized affine warp that accounts for the motion of smooth planar patches and compensates for changes in illumination.
TRA CY is a prototype of a middleware architecture that supports the migration of agents tin our definition: Self contained, autonomous objects) in heterogeneous networks withthe aim to complement more traditional di...
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ISBN:
(纸本)0769510868
TRA CY is a prototype of a middleware architecture that supports the migration of agents tin our definition: Self contained, autonomous objects) in heterogeneous networks withthe aim to complement more traditional distributed architectures. TRACY supports a weak form of (optimized) agent migration in a network of agent servers and implements local message passing between agents. Derived from a concise evaluation of requirements, mostly targeted towards eCommerce and intranet applications, TRACY is based on a three layer architecture model that supports a clean separation of concerns. A fully functional prototype of TRACY is by now ready for a first release and will be offered to system developers on the basis of an open-source venture. Currently, we are developing an industrial strength reference installation with a partner in rite transport and logistics domain. the focus of this paper are the lessons learned during requirements analysis and system,ll design, and the architecture of TRACY.
this paper discusses the issues related to the correctness of agile manufacturing systems with distributed architectures. the corresponding development of softwareengineering methods targets the goal of easy-re-confi...
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this paper discusses the issues related to the correctness of agile manufacturing systems with distributed architectures. the corresponding development of softwareengineering methods targets the goal of easy-re-configurable software self-organized similar to that of the hardware. However, the existing methods of software validation (manual testing or computer-aided simulation) are too slow to keep up with a pace of reconfigurations. In this paper we present an approach and a software tools to incorporate the formal verification to the practice of control engineering. the software package "Verification Environment for Distributed Applications" (VEDA) has been developed for model-based simulation and verification united by a homogeneous graphical user interface. Net Condition Event systems (NCES) are used for modeling. VEDA deals with distributed controllers as defined in IEC61499 and automatically generates the formal model of the controller given its source code.
Designers of safety-critical real-time systems are often mandated by requirements on reliability as well as timing guarantees. For guaranteeing timing properties, the standard practice is to use various analysis techn...
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ISBN:
(纸本)0780372417
Designers of safety-critical real-time systems are often mandated by requirements on reliability as well as timing guarantees. For guaranteeing timing properties, the standard practice is to use various analysis techniques provided by hard real-time scheduling theory. However, in many cost conscious industries, such as automotive, it is imperative that the designers also adhere to policies that reduce system resources to the extent feasible. From a reliability and cost perspective there is a trade-off between timing guarantees, the level of hardware and software faults, and the per-unit cost. By allowing occasional deadline misses, less costly hardware may be used, while still meeting the overall reliability requirement. this paper presents analysis based on simulation, that considers the effects of faults and timing parameter variations on schedulability analysis, and its impact on the reliability estimation of the system. We look at a wider set of scenarios than just the worst case considered in hard real-time schedulability analysis. the ideas have general applicability, but the method has been developed with modelling the effects of external interferences on the Controller Area Network (CAN) in mind. We illustrate the method by showing that a CAN interconnected distributed system, subjected to external interference, may be proven to satisfy its timing requirements with a sufficiently high probability, even in cases when the worst-case analysis has deemed it non-schedulable.
Recently much effort has been spent on providing a shared address space abstraction on clusters of small-scale symmetric multiprocessors. However, advances in technology will soon make it possible to construct these c...
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this paper presents a system for analog filter design. the system consists of a special library of functions, SYNTFIL, for the MAPLE environment which allows both approximation, computation and consecutive synthesis o...
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this paper presents a system for analog filter design. the system consists of a special library of functions, SYNTFIL, for the MAPLE environment which allows both approximation, computation and consecutive synthesis of an electrical circuit. A WWW interface for the complex design of filters is then presented. the WWW interface uses the above mentioned MAPLE software. the system is proposed for education in the CTU, Faculty of Electrical engineering.
Conditional capture and conditional precharge techniques for high-performance flip-flops are reviewed in terms of power and delay. It is found that application of conditional techniques can improve energy-delay produc...
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Conditional capture and conditional precharge techniques for high-performance flip-flops are reviewed in terms of power and delay. It is found that application of conditional techniques can improve energy-delay product for up to 14% for 50% input activity and save more than 50% in power consumption for quiet input. this property makes conditional methods suitable for high-performance VLSI systems.
In this paper, an emulation engine for educational microprocessor application boards is presented. A widely used application board, DIGIAC D2000, is emulated. In addition, features comparison between the DIGIAC D2000 ...
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In this paper, an emulation engine for educational microprocessor application boards is presented. A widely used application board, DIGIAC D2000, is emulated. In addition, features comparison between the DIGIAC D2000 and its emulated counterpart is included. Expansion possibilities providing wider applicability are examined. A model for further enhancements and add-ons is also discussed.
Symmetric variables have been used extensively to simplify design and synthesis of digital circuits. Methods to detect symmetric variables as well as special methods for synthesis and design of highly symmetric functi...
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Symmetric variables have been used extensively to simplify design and synthesis of digital circuits. Methods to detect symmetric variables as well as special methods for synthesis and design of highly symmetric functions have been continuously investigated. In this paper the author identifies and describes new, generalized symmetric relations between variables of Boolean functions. A method to detect and identify these symmetries is presented, and results showing the existence of such symmetries in MCNC benchmark functions are given. Possible applications are discussed.
An asynchronous VLSI implementation of the international Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design, a synchronous version of the algorithm was also desig...
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An asynchronous VLSI implementation of the international Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design, a synchronous version of the algorithm was also designed. the VHDL hardware description language was used in order to describe the algorithm. By using Synopsys commercially available tools, the VHDL code was synthesized. After placing and routing, both designs were fabricated with 0.6 /spl mu/m CMOS technology. With a system clock of up to 8 MHz and a power supply of 5 V, the two chips were tested and evaluated, comparing them withthe software implementation of the IDEA algorithm. this new approach proves efficiently the lower power consumption of the asynchronous implementation compared to the existing synchronous one. therefore the asynchronous chip performs efficiently in WEP (Wireless Encryption Protocols) and high speed networks.
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