Multicore processors can deliver higher performance than single-core processors by exploiting thread level parallelism (TLP): applications are split into independent threads, each of which is mapped into a different c...
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Smart phones are starting to find use in mission critical applications, such as search-and-rescue operations, wherein the mission capabilities are realized by deploying a collaborating set of services across a group o...
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To avoid data cache trashing between heap-allocated data and other data areas, a distinct object cache has been proposed for embedded real-time Java processors. this object cache uses high associativity in order to st...
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In this paper, we present a prototype of the real-time Systems Compiler (RTSC). the RTSC is a compiler-based tool that enables the migration from event-triggered to time-triggered real-time systems. this is achieved b...
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In this paper, we present a prototype of the real-time Systems Compiler (RTSC). the RTSC is a compiler-based tool that enables the migration from event-triggered to time-triggered real-time systems. this is achieved by replacing the real-time systems architecture of a given real-time system. the real-time systems architecture governs the structural properties of the white-box view of a real-time system: how are tasks attached to events and how are dependencies between different tasks implemented. the RTSC uses an abstraction called Atomic Basic Blocks (ABBs) to hide the real-time systems architecture and capture all relevant dependencies of an event-triggered system in a global ABB-graph. the RTSC automatically extracts that ABB-graph from an event-triggered real-time system given as source code, transforms that ABB-graph appropriately, and maps it to a statically computed schedule that could be executed by standard time-triggered real-time operating systems. Important temporal properties of the physical environment of the real-time system needed for that transformation are stored in a system model provided as additional input to the RTSC. Furthermore, we demonstrate the applicability of our approach and the operation of our prototype by transforming an event-triggered control application into a time-triggered equivalent. Copyright (C) 2011 John Wiley & Sons, Ltd.
In this paper, we present a prototype of the real-time Systems Compiler (RTSC). the RTSC is a compiler-based tool that enables the migration from event-triggered to time-triggered real-time systems. this is achieved b...
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In this paper, we present a prototype of the real-time Systems Compiler (RTSC). the RTSC is a compiler-based tool that enables the migration from event-triggered to time-triggered real-time systems. this is achieved by replacing the real-time systems architecture of a given real-time system. the real-time systems architecture governs the structural properties of the white-box view of a real-time system: how are tasks attached to events and how are dependencies between different tasks implemented. the RTSC uses an abstraction called Atomic Basic Blocks (ABBs) to hide the real-time systems architecture and capture all relevant dependencies of an event-triggered system in a global ABB-graph. the RTSC automatically extracts that ABB-graph from an event-triggered real-time system given as source code, transforms that ABB-graph appropriately, and maps it to a statically computed schedule that could be executed by standard time-triggered real-time operating systems. Important temporal properties of the physical environment of the real-time system needed for that transformation are stored in a system model provided as additional input to the RTSC. Furthermore, we demonstrate the applicability of our approach and the operation of our prototype by transforming an event-triggered control application into a time-triggered equivalent. Copyright (C) 2011 John Wiley & Sons, Ltd.
Static cache analysis for data allocated on the heap is practically impossible for standard data caches. We propose a distinct object cache for heap allocated data. the cache is highly associative to track symbolic ob...
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Static cache analysis for data allocated on the heap is practically impossible for standard data caches. We propose a distinct object cache for heap allocated data. the cache is highly associative to track symbolic object addresses in the static analysis. Cache lines are organized to hold single objects and individual fields are loaded on a miss. this cache organization is statically analyzable and improves the performance. In this paper we present the design and implementation of the object cache in a uniprocessor and chip-multiprocessor version of the Java processor JOP.
Integration of system components is a crucial challenge in the design of embedded real-time systems, as complex non-functional interdependencies may exist. [20] presented a framework, enabling autonomous verification ...
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Integration of system components is a crucial challenge in the design of embedded real-time systems, as complex non-functional interdependencies may exist. [20] presented a framework, enabling autonomous verification of timing properties in the system itself. the work presented in this paper, takes that approach one step further, enabling autonomuous assignment of execution priorities under timing constraints. We present a distributed heuristic algorithm for the constraint statisfaction problem (CSP) of finding feasible priority assignments in static priority preemptive (SPP) scheduled hard real-time systems. the proposed heuristic considers end-to-end path latency constraints in arbitrary task graphs mapped on arbitrary platform graphs.
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