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Hardware multicast routing algorithm for two-dimensional meshes

Hardware multicast routing algorithm for two-dimensional mes...

引用

Proceedings of the 1996 8th ieee symposium on parallel and distributed processing

作者： Mohapatra, Prasant Varavithya, Vara Iowa State Univ Ames United States

Multicast communication is a significant operation in multicomputer systems and can be used to support several other collective communication operations. Hardware implementation is a viable solution to develop a low latency multicast algorithm. In this paper, we present a new multicast routing algorithm for two-dimensional meshes. the algorithm uses worm-hole routing mechanism and can send messages to any number of destinations within two start-up communication phases;hence the name, two-phase multicast (TPM) algorithm. the algorithm uses the base routing scheme used for unicast communication, thus minimizing the additional hardware support. the algorithm allows some intermediate nodes that are not in the destination set to perform multicast functions. this feature allows flexibility in multicast path selection and therefore improves the performance. A simulation study has been conducted to investigate the performance of the purposed TPM algorithm. the simulation results show that the proposed TPM algorithm performs significantly better for both contention-free and mixed-traffic conditions, when compared with the previously proposed multicast algorithms.

关键词： parallel processing systems

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Java ProActive vs. Fortran MPI: Looking at the future of parallel Java

Java ProActive vs. Fortran MPI: Looking at the future of par...

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10th Workshop on Advances in parallel and distributed Computational Models/22nd ieee International parallel and distributed processing symposium

作者： Amedro, Brian Caromel, Denis Huet, Fabrice Bodnartchouk, Vladimir INRIA Sophia Antipolis CNRS I3S UNSA Sophia Antipolis France ActiveEon Nice France

ISBN: (纸本)9781424416936

About ten years after the Java Grande effort, this paper aims at providing a snapshot of the comparison of Fortran MPI, with Java performance for parallel computing, using the ProActive library. We first analyze some performance details about ProActive behaviors, and then compare its global performance from the MPI library. this comparative is based on the five kernels of the NAS parallel Benchmarks. From those experiments we identify benchmarks where parallel Java performs as well as Fortran MPI, and lack of performance on others, together with clues for improvement.

关键词： Benchmarking

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PHONOTACTIC SPOKEN LANGUAGE RECOGNITION: USING DIVERSELY ADAPTED ACOUSTIC MODELS IN parallel PHONE RECOGNIZERS

PHONOTACTIC SPOKEN LANGUAGE RECOGNITION: USING DIVERSELY ADA...

引用

8th International symposium on Chinese Spoken Language processing (ISCSLP)

作者： Leung, Cheung-Chi Ma, Bin Li, Haizhou ASTAR Inst Infocomm Res Singapore 138632 Singapore

ISBN: (纸本)9781467325073;9781467325066

In phonotactic spoken language recognition systems, acoustic model adaptation prior to phone lattice decoding has been adopted to deal with the mismatch between training and test conditions. Moreover, combining diversified phonotactic features is commonly used. these motivate us to have an in-depth investigation of combining diversified phonotactic features from diversely adapted acoustic models. Our experiment shows that our approach achieves an equal error rate (EER) of 1.94% in the 30-second closed-set trials of the 2007 NIST Language Recognition Evaluation (LRE). It represents a 14.9% relative improvement in EER over a sophisticated system, in which parallel phone recognizers, speaker adaptive training (SAT) in acoustic models and CMLLR adaptation are used. Moreover, it is shown that our approach provides consistent and substantial improvements in three different phonotactic systems, in each of which a single phone recognizer is used.

关键词： MLLR adaptation phone recognizer phone lattice spoken language recognition

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MPI code encapsulating using parallel CORBA object

MPI code encapsulating using parallel CORBA object

引用

Proceedings of the 1999 8th ieee International symposium on High Performance distributed Computing - HPDC-8

作者： Rene, Christophe Priol, thierry IRISA/IFSIC Rennes France

this paper describes a technique that allows an MPI code to be encapsulated into a component. Our technique is based on an extension to the Common Object Request Broker Architecture (CORBA) from the OMG (Object Management Group). the proposed extensions do not modify the CORBA core infrastructure (the Object Request Broker) so that it can fully co-exist with existing CORBA applications. An MPI code is seen as a new kind of CORBA object that hides most of the cumbersome problems when dealing with parallelism. Such technique can be used to connect MPI codes to existing CORBA software infrastructures which are now being developed in the framework of several research and development projects such as JACO3, JULIUS or TENT from DLR. To illustrate the concept of parallel CORBA object, we present a virtual reality application that is made of the coupling of a light simulation application (radiosity) and a visualization tool using VRML and Java.

关键词： parallel processing systems

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Fault tolerance protocols for parallel programs based on tasks replication

Fault tolerance protocols for parallel programs based on tas...

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8th International symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems

作者： Aguilar, J Hernández, M Univ Los Andes Fac Ingn Dpto Comp CEMISID Merida 5101 Venezuela

ISBN: (纸本)076950728X

In this work we propose a fault-tolerant mechanism for parallel programs based on task replication. We use a sequential discrete-event simulator of a distributed system subject to failures to compare a semi-active approach and a passive approach of the protocol. In our model, each time a task of a given parallel program is allocated, a copy of it is stored in a second processor, called the buddy processor. If the original processor fails, the copies of the tasks at the buddy processor will be processed, providing fault tolerance. Some performance measures, such as program execution times and processor utilization factors, are given for the different versions of the mechanism. the performance has been studied as a function of processor degradation, and program and system sizes.

关键词： Fault tolerant computer systems

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Almost complete address translation (ACATS) disk array declustering

Almost complete address translation (ACATS) disk array declu...

引用

Proceedings of the 1996 8th ieee symposium on parallel and distributed processing

作者： thomas, J.E. Schwarz, S.J. Burkhard, Walter A. St. Louis Univ Saint Louis United States

We present a novel declustering scheme (ACATS) for reliability stripes in an orthogonal disk array. Our scheme is deterministic, run-time efficient, and provides frequently the best possible and always an almost best possible distribution of failure-induced incremental rebuild workloads. Our scheme provides protection against single disk as well as single string failures within the disk array. Our approach presents a framework in which the Level 5 RAID organization logically appears as a Level 4 RAID;it facilitates the provision of distributed sparing in exactly the same manner. ACATS does not require the existence of a suitably configured block design or of a run-time efficient pseudo-random number generator;it is applicable to arbitrarily configured orthogonal disk arrays. Our scheme is faster than declustering schemes that use pseudo-random permutations and achieves better uniformity of disk loads during a disk rebuild;it is simpler than schemes based on block designs. ACATS provides a rich spectrum of declustering schemes.

关键词： parallel processing systems

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Noise-Resilient Empirical Performance Modeling with Deep Neural Networks 35

Noise-Resilient Empirical Performance Modeling with Deep Neu...

引用

35th ieee International parallel and distributed processing symposium (IPDPS)

作者： Ritter, Marcus Geiss, Alexander Wehrstein, Johannes Calotoiu, Alexandru Reimann, thorsten Hoefler, Torsten Wolf, Felix Tech Univ Darmstadt Dept Comp Sci Darmstadt Germany Swiss Fed Inst Technol Dept Comp Sci Zurich Switzerland

ISBN: (纸本)9781665440660

Empirical performance modeling is a proven instrument to analyze the scaling behavior of HPC applications. Using a set of smaller-scale experiments, it can provide important insights into application behavior at larger scales. Extra-P is an empirical modeling tool that applies linear regression to automatically generate human-readable performance models. Similar to other regression-based modeling techniques, the accuracy of the models created by Extra-I' decreases as the amount of noise in the underlying data increases. this is why the performance variability observed in many contemporary systems can become a serious challenge. In this paper, we introduce a novel adaptive modeling approach that makes Extra-P more noise resilient, exploiting the ability of deep neural networks to discover the effects of numerical parameters, such as the number of processes or the problem size, on performance when dealing with noisy measurements. Using synthetic analysis and data from three different case studies, we demonstrate that our solution improves the model accuracy at high noise levels by up to 25% while increasing their predictive power by about 15%.

关键词： Performance analysis performance modeling deep learning artificial neural networks high performance computing parallel processing

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Framework for automatic dynamic data mapping

Framework for automatic dynamic data mapping

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Proceedings of the 1996 8th ieee symposium on parallel and distributed processing

作者： Garcia, Jordi Ayguade, Eduard Labarta, Jesus Universitat Politecnica de Catalunya Barcelona Spain

Physically-distributed memory multiprocessors are becoming popular and data distribution and loop parallelization are aspects that a parallelizing compiler has to consider in order to get efficiency from the system. the cost of accessing local and remote data can be one or several orders of magnitude different, and this can dramatically affect the performance of the system. It would be desirable to free the programmer from considerations of the low-level details of the target architecture, to program explicit processes or specify interprocess communication. In this paper, we present an approach to automatically derive static or dynamic data distribution strategies for the arrays used in a program. All the information required about data movement and parallelism is contained in a single data structure, called the Communication-parallelism Graph (CPG). the problem is modeled and solved using a general purpose linear 0-1 integer programming solver. this allows us to find the optimal solution for the problem for one-dimensional array distributions. We also show the feasibility of using this approach in terms of compilation time and quality of the solutions generated.

关键词： distributed computer systems

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A distributed location management scheme for mobile hosts

A distributed location management scheme for mobile hosts

引用

8th International Conference on parallel and distributed Systems (ICPADS 2001)

作者： Shankaran, R Vardharajan, V Hitchens, M Macquarie Univ Dept Comp N Ryde NSW Australia

ISBN: (纸本)0769511538

With the increasing growth in mobile with the increasing growth in mobile computing devices and wireless networks, users are able to access information from anywhere and at anytime. In such situations, the issues of location management for mobile hosts are becoming increasingly significant. Different location management schemes such as Columbia University's mobile IP scheme and IETF mobile IP have been proposed. In this paper, we propose a new distributed location management scheme and discuss the advantages of the proposed scheme over the others. the paper then considers the issues of multicasting in the proposed architecture.

关键词： distributed computer systems

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On optimal placements of processors in Tori networks

On optimal placements of processors in Tori networks

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Proceedings of the 1996 8th ieee symposium on parallel and distributed processing

作者： Blaum, Mario Bruck, Jehoshua Pifarre, Gustavo D. Sanz, Jorge L.C. IBM Almaden Research Cent San Jose United States

Two and three dimensional k-tori are among the most used topologies in the designs of new parallel computers. Traditionally (with the exception of the Tera parallel computer), these networks have been used as fully-populated networks, in the sense that every routing node in the topology is subjected to message injection. However, fully-populated tori and meshes exhibit a theoretical throughput which degrades as the network size increases. In contrast, multistage networks (that are partially populated) scale well with the network size. Introducing slackness in fully-populated tori, i.e., reducing the number of processors, and studying optimal routing strategies for the resulting interconnections are the central subjects of this paper. the key concept that we study is the placement of the processors in a network together with a routing algorithm between them, where a placement is the subset of the nodes in the interconnection network that are attached to processors. Our main contribution is the construction of optimal placements for d-dimensional k-tori networks, of sizes k and k2 and the corresponding routing algorithms for the cases d = 2 and d = 3, respectively.

关键词： parallel processing systems

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