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Fast community detection algorithm with GPUs and multicore architectures

Fast community detection algorithm with GPUs and multicore a...

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25th ieee International parallel and distributed processing symposium, IPDPS 2011

作者： Soman, Jyothish Narang, Ankur IBM Research India New Delhi India

ISBN: (纸本)9780769543857

In this paper, we present the design of a novel scalable parallel algorithm for community detection optimized for multi-core and GPU architectures. Our algorithm is based on label propagation, which works solely on local information, thus giving it the scalability advantage over conventional approaches. We also show that weighted label propagation can overcome typical quality issues in communities detected with label propagation. Experimental results on well known massive scale graphs such as Wikipedia (100M edges) and also on RMAT graphs with 10M - 40M edges, demonstrate the superior performance and scalability of our algorithm compared to the well known approaches for community detection. On the hep-th graph (352K edges) and the wikipedia graph (100M edges), using Power 6 architecture with 32 cores, our algorithm achieves one to two orders of magnitude better performance compared to the best known prior results on parallel architectures with similar number of CPUs. Further, our GPGPU based algorithm achieves 8x improvement over the Power 6 performance on 40M edge R-MAT graph. Alongside, we achieve high quality (modularity) of communities detected, with experimental evidence from well-known graphs such as Zachary karate club, Dolphin network and Football club, where we achieve modularity that is close to the best known alternatives. To the best of our knowledge these are best known results for community detection on massive graphs (100M edges) in terms of performance and also quality vs. performance trade-off. this is also a unique work on community detection on GPGPUs with scalable performance. © 2011 ieee.

关键词： parallel architectures

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Scheduling parallel iterative applications on volatile resources

Scheduling parallel iterative applications on volatile resou...

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25th ieee International parallel and distributed processing symposium, IPDPS 2011

作者： Casanova, Henri Dufossé, Fanny Robert, Yves Vivien, Frédéric University of Hawai'i at Manoa United States Ecole Normale Supérieure de Lyon France

ISBN: (纸本)9780769543857

In this paper we study the execution of iterative applications on volatile processors such as those found on desktop grids. We develop master-worker scheduling schemes that attempt to achieve good trade-offs between worker speed and worker availability. A key feature of our approach is that we consider a communication model where the bandwidth capacity of the master for sending application data to workers is limited. this limitation makes the scheduling problem more difficult both in a theoretical sense and in a practical sense. Furthermore, we consider that a processor can be in one of three states: available, down, or temporarily preempted by its owner. this preempted state also complicates the scheduling problem. In practical settings, e.g., desktop grids, master bandwidth is limited and processors are temporarily reclaimed. Consequently, addressing the aforementioned difficulties is necessary for successfully deploying master-worker applications on volatile platforms. Our first contribution is to determine the complexity of the scheduling problem in its off-line version, i.e., when processor availability behaviors are known in advance. Even with this knowledge, the problem is NP-hard, and cannot be approximated within a factor 8/7. Our second contribution is a closed-form formula for the expectation of the time needed by a worker to complete a set of tasks. this formula relies on a Markovian assumption for the temporal availability of processors, and is at the heart of some heuristics that aim at favoring "reliable" processors in a sensible manner. Our third contribution is a set of heuristics, which we evaluate in simulation. Our results provide guidance to selecting the best strategy as a function of processor state availability versus average task duration. © 2011 ieee.

关键词： Bandwidth

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A MapReduce based parallel SVM for large scale spam filtering

A MapReduce based parallel SVM for large scale spam filterin...

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2011 8th International Conference on Fuzzy Systems and Knowledge Discovery, FSKD 2011, Jointly with the 2011 7th International Conference on Natural Computation, ICNC'11

作者： Caruana, Godwin Li, Maozhen Qi, Man School of Engineering and Design Brunel University Uxbridge Middlesex UB8 3PH United Kingdom Department of Computing Canterbury Christ Church University Canterbury Kent CT1 1QU United Kingdom Key Laboratory of Embedded Systems and Service Computing Ministry of Education Tongji University China

ISBN: (纸本)9781612841816

Spam continues to inflict increased damage. Varying approaches including Support Vector Machine (SVM) based techniques have been proposed for spam classification. However, SVM training is a computationally intensive process. this paper presents a parallel SVM algorithm for scalable spam filtering. By distributing, processing and optimizing the subsets of the training data across multiple participating nodes, the distributed SVM reduces the training time significantly. Ontology based concepts are also employed to minimize the impact of accuracy degradation when distributing the training data amongst the SVM classifiers. © 2011 ieee.

关键词： Support vector machines

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Proceedings - 2011 ieee International Conference on High Performance Computing and Communications, HPCC 2011 - 2011 ieee International Workshop on Future Trends of distributed Computing Systems, FTDCS 2011 - Workshops of the 2011 International Conference on Ubiquitous Intelligence and Computing, UIC 2011 - Workshops of the 2011 International Conference on Autonomic and Trusted Computing, ATC 2011

Proceedings - 2011 IEEE International Conference on High Per...

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13th ieee International Workshop on FTDCS 2011, the 8th International Conference on ATC 2011, the 8th International Conference on UIC 2011 and the 13th ieee International Conference on HPCC 2011

ISBN: (纸本)9780769545387

the proceedings contain 142 papers. the topics discussed include: distributed caching strategies in peer-to-peer systems;a power-aware based storage architecture for high performance computing;a distributed reconfigurable active SSD platform for data intensive applications;a parallel processing scheme for large-size sliding-window applications;algebraic models for the cube connected cycles and shuffle exchange graphs;a high-performance and energy-efficient virtually tagged stack cache architecture for multi-core environments;providing quality of science in volunteer computing;an effective dynamic scheduling runtime and tuning system for heterogeneous multi and many-core desktop platforms;on the social aspects of personalized ranking for web services;stable adaptive work-stealing for concurrent multi-core runtime systems;rule pattern parallelization of packet filters on multi-core environments;and memory-intensive applications on a many-core processor.

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Novel PLL scheme for grid connection of three-phase power converters

Novel PLL scheme for grid connection of three-phase power co...

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8th ieee symposium on Diagnostics for Electrical Machines, Power Electronics and Drives, SDEMPED 2011

作者： López González, Osley Buja, Giuseppe Department of Electrical Engineering University of Padova Italy

ISBN: (纸本)9781424493036

Basic phase-locked loop (PLL) schemes used for the grid connection of three-phase static converters suffer from line voltage harmonics and unbalance. To overcome this shortcoming, the operation of the basic PLL schemes is improved by supplementing them with blocks that pre or post-processes the line voltages. this paper presents a novel improved PLL scheme that, in spite of its simplicity, offers excellent performance. the scheme is composed by two stages, namely a block, termed as SthFPSC, that rejects the harmonics and the negative-sequence component of the line voltages by processing the voltages in the stationary reference frame, and the basic PLL scheme formulated according to the instantaneous p-q power theory (pPLL). the capability of the SthFPSC block in extracting the fundamental harmonic of the positive-sequence component of the line voltages combined with the capability of the pPLL in synthesizing the grid angle give rise to a PLL scheme, termed as stationary reference frame improved pPLL (StI-pPLL), which joins the merits of the two constituent stages. After reviewing the basic and the main improved PLL schemes, the paper describes the StI-pPLL scheme. then the scheme is tested by simulation under distorted and unbalanced grid conditions to demonstrate its effectiveness. Comparison of the results to those obtained from the pPLL scheme improved in the traditional way points out the superior performance of the novel scheme. © 2011 ieee.

关键词： distributed power generation

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Power token balancing: Adapting CMPs to power constraints for parallel multithreaded workloads

Power token balancing: Adapting CMPs to power constraints fo...

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25th ieee International parallel and distributed processing symposium, IPDPS 2011

作者： Cebrián, Juan M. Aragón, Juan L. Kaxiras, Stefanos Dept. of Computer Engineering University of Murcia Murcia Spain Dept. of Information Technology University of Uppsala Uppsala Sweden

ISBN: (纸本)9780769543857

In the recent years virtually all processor architectures employ multiple cores per chip (CMPs). It is possible to use legacy (i.e., single-core) power saving techniques in CMPs which run either sequential applications or independent multithreaded workloads. However, new challenges arise when running parallel shared-memory applications. In the later case, sacrificing some performance in a single core (thread) in order to be more energy-efficient might unintentionally delay the rest of cores (threads) due to synchronization points (locks/barriers), therefore, harming the performance of the whole application. CMPs increasingly face thermal and power-related problems during their typical use. Such problems can be solved by setting a power budget to the processor/core. this paper initially studies the behavior of different techniques to match a predefined power budget in a CMP processor. While legacy techniques properly work for thread independent/multi-programmed workloads, parallel workloads exhibit the problem of independently adapting the power of each core in a thread dependent scenario. In order to solve this problem we propose a novel mechanism, Power Token Balancing (PTB), aimed at accurately matching an external power constraint by balancing the power consumed among the different cores using a power token-based approach while optimizing the energy efficiency. We can use power (seen as tokens or coupons) from non-critical threads for the benefit of critical threads. PTB runs transparent for thread independent / multiprogrammed workloads and can be also used as a spin lock detector based on power patterns. Results show that PTB matches more accurately a predefined power budget (total energy consumed over the budget is reduced to 8% for a 16-core CMP) than DVFS with only a 3% energy increase. Finally, we can trade accuracy on matching the power budget for energy-efficiency reducing the energy a 4% with a 20% of accuracy. © 2011 ieee.

关键词： Energy efficiency

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An energy-efficient scheduling algorithm for sporadic real-time tasks in multiprocessor systems

An energy-efficient scheduling algorithm for sporadic real-t...

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13th ieee International Workshop on FTDCS 2011, the 8th International Conference on ATC 2011, the 8th International Conference on UIC 2011 and the 13th ieee International Conference on HPCC 2011

作者： Zhang, Dong-Song Chen, Fang-Yuan Li, Hong-Hua Jin, Shi-Yao Guo, De-Ke National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China School of Computing Science Simon Fraser University 8888 University Drive Burnaby BC V5A 1S6 Canada National Laboratory for Information System Engineering School of Information Systems and Management National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769545387

As the energy consumption of embedded multiprocessor systems becomes increasingly prominent, the real-time energy-efficient scheduling in multiprocessor systems becomes an urgent problem to reduce the system energy consumption while meeting real-time constraints. For a multiprocessor with independent DVFS and DPM at each processor, this paper proposes an energy-efficient real-time scheduling algorithm named LRE-DVFS-EACH, based on LRE-TL which is an optimal real-time scheduling algorithm for sporadic tasks. LRE-DVFS-EACH utilizes the concept of TL plane and the idea of fluid scheduling to dynamically scale the voltage and frequency of processors at the initial time of each TL plane as well as the release time of a sporadic task in each TL plane. Consequently, LRE-DVFS-EACH can obtain a reasonable tradeoff between the real-time constraints and the energy saving. LRE-DVFS-EACH is also adaptive to the change of workload caused by the dynamic release of sporadic tasks, which can obtain more energy savings. the experimental results show that compared with existing algorithms, LRE-DVFS-EACH can not only guarantee the optimal feasibility of sporadic tasks, but also achieve more energy savings in all cases, especially in the case of high workloads. © 2011 ieee.

关键词： Real time systems

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Towards network-aware divisible load theory for optical grids

Towards network-aware divisible load theory for optical grid...

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13th ieee International Workshop on FTDCS 2011, the 8th International Conference on ATC 2011, the 8th International Conference on UIC 2011 and the 13th ieee International Conference on HPCC 2011

作者： Abouelela, Mohamed El-Darieby, Mohamed Software Systems Engineering Department University of Regina Regina SK Canada

ISBN: (纸本)9780769545387

Most grid applications require the processing of large amounts of data stored at different locations across the network which makes optical grid infrastructures optimal for such applications. the increase in intensity of data- and communications of these applications calls for new mechanisms and theories on how to optimally allocate optical grid resources. Typical Divisible Load theory (DLT) makes optimal allocation of computational resources. In this paper, we introduce Network Aware Divisible Load Algorithm (NADLA) that extends DLT to optimally allocate both the computational and networking resources of an optical grid. We assume a data- and communications-intensive application where data is stored at different sites across the optical grid and can be divided into independent subsets to be processed in parallel at different sites. the algorithm defines an optimal data transfer schedule that defines when to transfer what data subsets to which sites across the optical grid in order to minimize the overall application completion time. It consists of two phases. In the first phase, NADLA provide load distribution that minimizes application completion time taking into account network connectivity and computational and networking resources availability. Site connectivity is estimated by considering the bandwidth and the expected free time of all the links connecting this site to other sites. In the second phase, a simple greedy algorithm is used to allocate computational and networking resources. Extensive Simulations are conducted to examine the performance of the proposed algorithm for different application types and sizes, and different optical grid topologies. Simulation results show the advantages of the proposed algorithm over the traditional DLT approach for the category of applications considered. © 2011 ieee.

关键词： distributed computer systems

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Power supply system of DC/AC micro grid system

Power supply system of DC/AC micro grid system

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8th International Conference on Power Electronics - ECCE Asia: "Green World with Power Electronics", ICPE 2011-ECCE Asia

作者： Yukita, K. Ban, K. Goto, Y. Ichiyanagi, K. Hirose, K. Ushirokawa, T. Okui, Y. Takabayashi, H. Aichi Institute of Technology 1247 Yachigusa Yagusa Toyota 470-0392 Japan NTT Facilites Inc G.H.Y. Bldg. 2-13-1 Kitaotsuka Toshima-ku Tokyo 170-0004 Japan SANYO Denki Co. Ltd 812-3 Shimonogo Ueda Nagano 386-1211 Japan Shin-Kobe Electric Machinery Co. Ltd 1300-5 Hachiman Nabari Mie 518-0493 Japan

ISBN: (纸本)9781612849560

this paper proposes an AC/DC power supply system with DGs using the parallel processing method. the purpose of this system is to supply the power without connecting to the utility gird. the DGs consist of photovoltaic (PV), -and wind generators (WG), and the main energy source of this system is the DGs and the UPS battery. When the system does not get enough energy from the DGs, and the power supply of the battery runs out, this system connects to the utility grid and begins to charge the battery and supply to the load. In this study, we focused on the AC power supply and DC power supply from DGs. then, the converters of DGs use two types, DC/AC type and DC/DC type. the power supply system has been operated with the actual loads of 20 kW in the campus of the Aichi Institute of Technology. this paper reports on our study of DC and AC power supplies in the event of a system anomaly. © 2011 ieee.

关键词： distributed power generation

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distributed Agent-based Architecture for Management of Crisis Situations using Trusted Code Execution

Distributed Agent-based Architecture for Management of Crisi...

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8th International symposium on Applied Machine Intelligence and Informatics

作者： Hluchy, L. Balogh, Z. Gatial, E. Slovak Acad Sci Inst Informat Dept Parallel & Distributed Comp Bratislava Slovakia

ISBN: (纸本)9781424464227

this article proposes a distributed architecture designed for management of crisis situations were multiple actors are involved from various organizations with different competences and communicating over IP-based networks including wireless devices. In such settings requirements exist for secure communication and trusted collection of data from various sources. the role of agents in the proposed architecture is primarily coordinated collection of information. In respect to requirements the overall agent infrastructure must be a secure, robust and fail resistant system. Required level of trust for agents is based on a special hardware module which provides trusted computing functionality. In the article we describe such architecture in terms of detailed requirements, design and decomposition to subsystems. We also provide a sample scenario use case inspired by concrete crisis situation. the architecture herein described is being used in scope of an EU integrated project called Secricom therefore we briefly describe the integration points with other systems involved in the project. We conclude with current state of the architecture implementation and with further plans concerning the development of the described architecture.

关键词： Architecture

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