this paper describes the implementation of the self timed asynchronous router in a parallel machine. the heterogenous architecture of the machine is outlined, then the need for asynchronous operations is explained, an...
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this paper describes the implementation of the self timed asynchronous router in a parallel machine. the heterogenous architecture of the machine is outlined, then the need for asynchronous operations is explained, and the interest of an asynchronous network control. the specification and VLSI design of the router are exhibited with its measured performances.
the problem of the design and implementation of parallel metric tree indexes, called M-trees, is elaborated. Four different object declustering techniques are proposed and tested in order to get a sufficient evidence ...
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the problem of the design and implementation of parallel metric tree indexes, called M-trees, is elaborated. Four different object declustering techniques are proposed and tested in order to get a sufficient evidence needed for specifying the pros and cons of their application. In general, the obtained I/O speedup and scaleup levels are high. A way how to deal withthe CPU parallelism is also proposed and its speedup and scaleup experimentally tested.
Previous work has shown the power of massively parallel configurable hardware (NGEN, [1, 2]) in conjunction with dataflow architectures for the simulation of evolving populations. NGEN is a flexible computer hardware ...
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Previous work has shown the power of massively parallel configurable hardware (NGEN, [1, 2]) in conjunction with dataflow architectures for the simulation of evolving populations. NGEN is a flexible computer hardware for rapid custom-circuit simulation of fine grained physical processes via a massively parallel architecture, e. g. 144 hardware configurable field programmable gate arrays (FPGAs, XC4008, Xilinx). NGEN is optimized to implement dataflow architectures and systolic algorithms for large problems and is confectioned with high speed distributed SRAM, 144*8*256kBit - 15ns access time, on the chip-to-chip interconnect.
this project has looked at novel retrieval methods for a variety of legal documents using the DAP parallel processor. the system has three main components: the document selector: this may be either the DAPText index s...
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this project has looked at novel retrieval methods for a variety of legal documents using the DAP parallel processor. the system has three main components: the document selector: this may be either the DAPText index server or any other suitable retrieval engine. DAPText is a database indexing engine from Cambridge parallelprocessing which runs on the DAP 610C, a massively parallel Single Instruction Multiple Data (SIMD) processor;the object server or document retriever that returns the full text of selected documents;the graphical user interface (GUI) that manages the interactions. For example, it translates the user queries into a form appropriate for the retrieval engine being used and converts the retrieved documents from the database storage format into Hypertext Markup Language (HTML) for the Web.
A disjunctive deductive database (DDDB) is more general than the deductive database model since the former captures more information than the latter. Distributing a DDDB facilitates the splitting of queries of the dat...
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A disjunctive deductive database (DDDB) is more general than the deductive database model since the former captures more information than the latter. Distributing a DDDB facilitates the splitting of queries of the database into subqueries to enhance query processing since the answers to each subquery are computed only against those portions of the DDDB relevant to the subquery and can be generated in parallel. Evaluating these subqueries thus improves the response time of the system and reduces communication cost involved in evaluating the entire query. Existing literature on DDDBs does not include a well-designed horizontal fragmentation approach. In this paper, we propose a horizontal fragmentation approach for any given DDDB D based on the set of common user queries S of D from which a fragment is produced for each query Q in S. All the rules and ground facts in D required to answer Q are collected into a fragment F, and it is sufficient to evaluate Q against F alone to compute all answers to Q. Hence, the need to process fragments generated by the other queries of D is eliminated, and time and cost of unnecessary processing is saved.
Previous work (J.S. McCaskill et al., 1996; 1997) has shown the power of massively parallel configurable hardware (NGEN) in conjunction with dataflow architectures for the simulation of evolving populations. NGEN is a...
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Previous work (J.S. McCaskill et al., 1996; 1997) has shown the power of massively parallel configurable hardware (NGEN) in conjunction with dataflow architectures for the simulation of evolving populations. NGEN is a flexible computer hardware for rapid custom circuit simulation of fine grained physical processes via a massively parallel architecture, e.g. 144 hardware configurable field programmable gate arrays (FPGAs, XC4008, Xilinx). NGEN is optimized to implement dataflow architectures and systolic algorithms for large problems and is confectioned with high speed distributed SRAM, 144*8*256 kBit, 15ns access time, on the chip to chip interconnect. Microconfigurable FPGAs allow a further step to close the gap between micro electronics and biology on the information processing area. A design for a massively parallel microconfigurable computer (POLYP) is presented. It is designed to allow online evolution in hardware with significant locally controllable memory resources. It is also designed for high throughput dataflow applications with large problem size. Additionally, an evolvable interface between high rate measurement devices is provided to allow adaptive processing coupled with real time experimental environments. the computer represents the next logical step towards evolvable hardware interacting with biology beyond the massively parallel computer NGEN.
An efficient technique for mapping arbitrarily large Bayesian belief networks on hypercubes with deadlock free implementation is presented. this technique shows that the speedup does not vary withthe number of nodes ...
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ISBN:
(纸本)0818676833
An efficient technique for mapping arbitrarily large Bayesian belief networks on hypercubes with deadlock free implementation is presented. this technique shows that the speedup does not vary withthe number of nodes in Bayesian network and is limited by the height of the Peot-Shachter tree. this technique also shows that the overhead in implementing Bayesian networks on parallel machines like hypercubes can be large.
Recently, there has been growing interest in simultaneous exploitation of task and data parallelism in scientific applications and in compiler and runtime support of this combined form of parallelism. In this paper we...
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ISBN:
(纸本)0818676833
Recently, there has been growing interest in simultaneous exploitation of task and data parallelism in scientific applications and in compiler and runtime support of this combined form of parallelism. In this paper we report on the integration of task and data parallelism on an important irregular application from the VLSI computer-aided design field namely VLSI layout verification. We report on the implementation, and experimental results of our study on a SUN Sparcserver 1000 shared memory multiprocessor a CM-5 distributed memory multiprocessor.
Efficient divide and conquer algorithms can be mapped to a parallel computer using either Task parallelism or Data parallelism. the former involves significant data movement and the latter can lead to severe load imba...
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ISBN:
(纸本)0818676833
Efficient divide and conquer algorithms can be mapped to a parallel computer using either Task parallelism or Data parallelism. the former involves significant data movement and the latter can lead to severe load imbalances. III this paper a new strategy is proposed, which we call Concatenated parallelism,for efficient parallel solution of problems resulting in divide and conquer trees. Our strategy is useful when the communication rime due to data movement in distributing the subproblems is significant in comparison to the rime required for subdivision.
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