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Impact of load balancing on unstructured adaptive grid computations for distributed-memory multiprocessors

Impact of load balancing on unstructured adaptive grid compu...

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International symposium on parallel and distributed processing (IPDPS)

作者： A. Sohm R. Biswas H.D. Simon Dept. of Comput. & Inf. Sci. New Jersey Inst. of Technol. Newark NJ USA RIACS NASA Ames Research Center Moffett Field CA USA NERSC Lawrence Berkeley National Laboratory Berkeley CA USA

the computational requirements for an adaptive solution of unsteady problems change as the simulation progresses. this causes workload imbalance among processors on a parallel machine which, in turn, requires significant data movement at runtime. We present a new dynamic load-balancing framework, called JOVE, that balances the workload across all processors with a global view. Whenever the computational mesh is adapted, JOVE is activated to eliminate the load imbalance. JOVE has been implemented on an IBM SP2 distributed-memory machine in MPI for portability. Experimental results for two model meshes demonstrate that mesh adaption with load balancing gives more than a sixfold improvement over one without load balancing. We also show that JOVE gives a 24-fold speedup on 64 processors compared to sequential execution.

关键词： Load management distributed computing Grid computing Runtime Computational fluid dynamics Computational modeling Computational Intelligence Society Space technology NASA Laboratories

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Sorting N items using a p-sorter in optimal time

Sorting N items using a p-sorter in optimal time

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International symposium on parallel and distributed processing (IPDPS)

作者： S. Olarin S.Q. Zheng Dept. of Comput. Sci. Old Dominion Univ. Norfolk VA USA Department of Computer Science Louisiana State University Baton Rouge LA USA

A sorting device capable of sorting p items in constant time is called a p-sorter. It is known that the task of sorting N items using a p-sorter requires at least /spl Omega/ (N log N/p log p) applications of the p-sorter. this bound is tight: there exist algorithms that use O (N log N/p log p) calls to the p-sorter to sort N items. However, there is no known implementable algorithm that can sort N items in O(N log N/p log p) time using a p-sorter. the main contribution of this paper is to propose a simple VLSI architecture and to show that in our architecture N items can be sorted in O(N log N/p log p) calls to the p-sorter, while enforcing conflict-free memory accesses. An important feature of our design is that the total additional VLSI area for hardware, other than the memory for data and the p-sorter, is kept to a minimum.

关键词： Sorting Very large scale integration Computer architecture Computer science Semiconductor device measurement Application software Hardware parallel algorithms parallel processing parallel architectures

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distributed list coloring: how to dynamically allocate frequencies to mobile base stations

Distributed list coloring: how to dynamically allocate frequ...

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International symposium on parallel and distributed processing (IPDPS)

作者： N. Garg M. Papatriantafilou P. Tsigas Max Planck Institute of Computer Science Saarbrucken Germany

To avoid signal interference in mobile communication it is necessary that the channels used by base stations for broadcast communication within their cells are chosen so that the same channel is never concurrently used by two neighboring stations. We model this channel allocation problem as a generalized list coloring problem and we provide two distributed solutions which are also able to cope with crash failures by limiting the size of the network affected by a faulty station in terms of the distance from that station. Our first solution uses a powerful synchronization mechanism to achieve a response time that depends only on /spl Delta/, the maximum degree of the signal interference graph, and a failure locality of 4. Our second solution is a simple randomized solution in which each node can expect to pick f/(4/spl Delta/) colors where f is the size of the list at the node; the response time of this solution is a constant and the failure locality 1. Besides being efficient (their complexity measures involve only small constants), the protocols presented in this work are simple and easy to apply in practice, provided the existence of distributed infrastructure in networks that are in use.

关键词： Radio spectrum management Interference Mobile communication Delay Base stations Broadcasting Channel allocation Computer crashes Frequency synchronization Protocols

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parallel algorithms for fast computation of normalized edit distances

Parallel algorithms for fast computation of normalized edit ...

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International symposium on parallel and distributed processing (IPDPS)

作者： O. Egecioglu M. Ibel Department of Computer Science University of California Santa Barbara CA USA

the authors give work-optimal and polylogarithmic time parallel algorithms for solving the normalized edit distance problem. the normalized edit distance between two strings X and Y with lengths n/spl ges/m is the minimum quotient of the sum of the costs of edit operations transforming X into Y by the length of the edit path corresponding to those edit operations. Marzal and Vidal (1993) proposed a sequential algorithm with a time complexity of O(nm/sup 2/). they show that this algorithm can be parallelized work-optimally on an array of n (or m) processors, and on a mesh of n/spl times/m processors. they then propose a sublinear time algorithm that is almost work-optimal: using O(mn/sup 1.75/) processors, the time complexity of the algorithm is O(n/sup 0.75/ log n) and the total number of operations is O (mn/sup 2.5/ log n). this algorithm runs on a CREW PRAM, but is likely to work on weaker PRAM models and hypercubes with minor modifications. Finally, they present a polylogarithmic O(log/sup 2/ n) time algorithm based on matrix multiplication which runs on a O(n/sup 6//log n) processor hypercube.

关键词： parallel algorithms Concurrent computing Signal processing algorithms Costs Phase change random access memory Hypercubes Dynamic programming Information retrieval Computer science parallel programming

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Index-shuffle graphs

Index-shuffle graphs

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International symposium on parallel and distributed processing (IPDPS)

作者： M. Baumslag B. Obrenic Bear Stearns and Company Inc. New York NY USA Department of Computer Science CUNY Flushing NY USA

Index-shuffle graphs are introduced as candidate interconnection networks for parallel computers. the comparative advantages of index-shuffle graphs over the standard bounded-degree "approximations" of the hypercube, namely butterfly-like and shuffle-like graphs, are demonstrated in the theoretical framework of graph embedding and network emulations. An N-node index-shuffle graph emulates: (1) an N-node shuffle-exchange graph with no slowdown, while the currently best emulations of shuffle-like graphs by hypercubes and butterflies incur a slowdown of /spl Omega/(log N); (2) its like-sized butterfly graph with a slowdown O(log log log N), while the currently best emulations of butterfly-like graphs by shuffle-like graphs incur a slowdown of /spl Omega/(log log N); (3) an N-node hypercube that executes an on-line leveled algorithm with a slowdown O(log log N) and without data circulation, while the slowdown of currently best such emulations of the hypercube by its bounded-degree shuffle-like and butterfly-like derivatives remains /spl Omega/(log N), and only if the entire local data set of every processor is allowed to circulate through the network.

关键词： Hypercubes Concurrent computing Emulation parallel architectures Computer networks Computational modeling Multiprocessor interconnection networks Computer science Educational institutions Physics

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parallel logic simulation on a network of workstations using PVM

Parallel logic simulation on a network of workstations using...

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International symposium on parallel and distributed processing (IPDPS)

作者： M. Kormicki A. Mahmood B.S. Carlson Washington State University Tri-Cities Richland WA USA Computer Science and Engineering University of Bridgeport Bridgeport CT USA State University of New York Stony Brook Stony Brook NY USA

parallel processing is recognized as a practical way to achieve high performance in logic simulation. Instead of using high cost parallel computers or special purpose hardware simulation engines, we explore the implementation of parallel logic simulation on an existing network of workstations using parallel Virtual Machine (PVM). We carry out a novel parallel implementation of an output event-driven logic simulation algorithm such that a global control processor or workstation is not needed to synchronize the advancement of simulation time to the next time step. Further advantages of our new approach include a random partitioning of the circuit on to available workstations and a pipelined execution of the different phases of the simulation algorithm. To achieve a better load balance we employ a semi-optimistic scheme for gate evaluations such that no rollback is required. the performance of our implementation has been evaluated in real time using the ISCAS combinational and sequential benchmark circuits. Speedups obtained improve with the size of the circuit and the activity level in the circuit. Analyses of the communication overhead shows that the techniques developed here will yield even higher gains as newer networking technologies such as fast and switched Ethernet or ATM are employed to connect workstations.

关键词： Logic Workstations Computational modeling Circuit simulation Computer simulation Discrete event simulation Partitioning algorithms parallel processing Costs Computer networks

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B/sup mad/-tree: an efficient data structure for parallel processing

B/sup mad/-tree: an efficient data structure for parallel pr...

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International symposium on parallel and distributed processing (IPDPS)

作者： S.K. Das M.A. Demuynck Department of Computer Sciences University of North Texas Denton TX USA Department of Math and Computer Science Texas Woman's University Denton TX USA

B-trees are used for accessing large database files, stored in lexicographic order on the secondary storage devices. Algorithms for concurrent B-tree data structures achieve only limited speedup when implemented on a parallel computer. To improve the performance, we propose a variant of the B/sup link/-tree, called the B/sup mad/-tree, which allows insertion without node splits, with multiple access in its leaf nodes, and dilation in both the index and the leaf nodes. parallel algorithms for search, insert and restructuring are designed for partitioned, locked and distributed models. Only part of an insertion node is locked during the insert, and simultaneous insertions by multiple processors in the same node are allowed. A restructuring algorithm runs periodically in the background and requires at most one wait by any search or update operation. Our implementations demonstrate that the B/sup mad/-tree algorithms outperform the best known B/sup link/-trees, and compare favorably with linear hashing. We achieve good speedup (e.g., 4.79 with 8 processors) for partitioned algorithms, and moderate speedup (2.49 with 8 processors) for locked algorithms, even including overhead costs. the insert times obtained for B/sup mad/-trees are 50% to 60% less than that for the B/sup link/-trees in partitioned implementations, and 70% to 80% less in locked implementations. the speedup results on the distributed memory platform (a network of workstations) were not that encouraging due to high communication costs.

关键词： Data structures parallel processing Costs Analytical models Partitioning algorithms Workstations Computer science Phase detection Joining processes Cache memory

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the active-ray approach to rendering on distributed memory multiprocessors

The active-ray approach to rendering on distributed memory m...

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International symposium on parallel and distributed processing (IPDPS)

作者： A. Law R. Yagel Department of Computer and Information Science Ohio State Uinversity USA

Object dataflow is a popular approach used in parallel rendering. the data representing the 3D scene is statically distributed among processors and objects are fetched and cached only on demand. Most previous object dataflow methods were implemented on shared memory architectures and exploited spatial coherency to reduce hardware cache misses. We propose an efficient model for object dataflow parallel volume rendering on message passing machines. the active ray tracing algorithm is introduced and its ray storage mechanism is used to support latency hiding by postponing computation on inactive rays. Memory usage is optimized by letting objects migrate and replicate at different processors rather than the common static assignments. Our cache-only-memory approach uses a distributed-directory scheme to trace the location of objects at other nodes. A mechanism to minimize network congestion was implemented which optimizes channel utilization. Unlike previous methods, our approach can benefit from temporal coherence and effectively minimizes communication costs in successive frames. We implemented a volume ray casting instance of the algorithm on the Cray T3D and achieved higher efficiency and scalability than existing algorithms. We achieve interactive frame rates of approximately 20 Hz for 128/sup 3/ volume, and 4 Hz for 256/sup 3/ volume on 128 processors.

关键词： Layout Memory architecture Spatial coherence Hardware Message passing Ray tracing Delay Costs Casting Scalability

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Efficient algorithms for block-cyclic redistribution of arrays

Efficient algorithms for block-cyclic redistribution of arra...

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International symposium on parallel and distributed processing (IPDPS)

作者： Young Won Lim P.B. Bhat V.K. Prasanna Department of EE-Systems University of Southern California Los Angeles CA USA

We present new algorithmic techniques for a classical research problem, runtime redistribution of an array from one block-cyclic layout to another. Our methodology for reducing communication overheads is based on a generalized circulant matrix formalism. Using this formalism, we derive direct, indirect, and hybrid communication schedules for the cyclic redistribution problem when the block size changes by an integer factor K. We have also developed formulae to estimate the timing performance of each of these schedules for a given parallel machine and redistribution problem. In our indirect communication schedule, blocks are moved from a source processor to a destination processor through intermediate "relay" processors. this reduces the number of communication steps by an order of magnitude, in comparison with previous approaches. this algorithm performs cyclic(x) to cyclic(Kx) redistribution on P processors in [log/sub 2/K]+2 steps. Implementations of these algorithms on the Cray T3D and on the IBM SP-2 show superior performance over previous approaches. Since our algorithms are developed using MPI, they can be easily ported to different application environments. Our techniques can be used in the design of scalable redistribution libraries, in efficient implementations of the REDISTRIBUTE directive of HPF and in developing parallel algorithms for various HPC applications.

关键词： Signal processing algorithms Processor scheduling parallel machines Algorithm design and analysis Libraries parallel algorithms High performance computing Program processors Programming profession Search problems

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Embedding of k-ary complete trees into hypercubes with optimal load

Embedding of k-ary complete trees into hypercubes with optim...

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International symposium on parallel and distributed processing (IPDPS)

作者： J. Trdlicka P. Tvrdik Department of Computer Science and Engineering Czech Technical University Prague Czech Republic

the main result of the paper is an algorithm for embedding k-ary complete trees into hypercubes with optimal load and asymptotically optimal dilation. the algorithm is fully scalable, the dimension of the hypercube can be chosen independently of the arity and height of the complete tree. the basic property of the embedded tree is that both all the tree nodes at a given level and all the tree nodes together are uniformly distributed within equally-sized subcubes of the hypercube. this implies that no hypercube node is loaded with more than [A/sub h//2/sup n/] tree nodes and [B/sub h//2/sup n/] leaves of the tree, where A/sub h/ is the number of all tree nodes, B/sub h/ is the number of leaves of the k-ary complete tree of height h, and n is the dimension of the hypercube. the embedding enables optimal emulations of both divide and conquer computations on the k-ary complete tree, where only one level of nodes is active at a time, and general computations based on k-ary complete trees, where all tree nodes are active simultaneously. As a special case the authors obtain an algorithm for embedding the k-ary complete tree of height h into its optimal hypercube with load 1 and with dilation that is only by a small constant factor worse than the lower bound. this improves the best previous result by Shen et al. (1995), whose embedding has load 1 and nearly optimal dilation, but requires much larger than the optimal hypercube.

关键词： Hypercubes Emulation Binary trees Computer science Embedded computing Multiprocessor interconnection networks Computer networks Concurrent computing Network topology parallel machines

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