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A hierarchical processor scheduling policy for multiprocessor systems

A hierarchical processor scheduling policy for multiprocesso...

引用

International symposium on parallel and distributed processing (IPDPS)

作者： S. Ayachi S.P. Dandamudi Nortel Inc. Ottawa ONT Canada School of Computer Science Carleton University Ottawa ONT Canada

Processor scheduling policies can be broadly divided into space-sharing and time-sharing policies. Space-sharing policies partition system processors and each partition is allocated exclusively to a job. In time-sharing policies, processors are temporally shared by jobs (e.g., in a round robin fashion). Equipartition is a dynamic space-sharing policy that has been proposed and studied extensively. Among the time-sharing policies, job-based round robin policy (RRJob) has been shown to be a very good policy. Performance analysis of these two policies suggests that Equipartition policy performs well at low to moderate system loads and is extremely sensitive to system overheads and variance in service demand of jobs. RRJob performs better when there is a high variance in service demand and at high system loads. Furthermore, these policies have been proposed for small-scale shared-memory systems and require a central run queue and/or central scheduler. the central queue/scheduler poses serious scalability problems for large-scale multiprocessor systems. We propose a new multiprocessor scheduling policy that combines the merits of space-sharing and time-sharing policies while eliminating the contention for the central queue/scheduler. the new policy, called hierarchical scheduling policy (HSP), uses a hierarchical run queue organization to take advantage of both temporal and spatial partitioning to allocate processing power amongst jobs waiting for service. We show that the HSP policy is considerably better than the purely space-sharing and purely time-sharing policies over a wide range of system parameters.

关键词： Multiprocessing systems Time sharing computer systems Processor scheduling Round robin parallel processing Performance analysis Large-scale systems Scalability Job listing service Computer science

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Deterministic permutation routing on a reconfigurable mesh

Deterministic permutation routing on a reconfigurable mesh

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International symposium on parallel processing

作者： A. Kapoor H. Schroder B. Beresford-Smith Department of E & C Engg. University of Newcastle Callaghan NSW Australia Department of CS University of Newcastle Callaghan NSW Australia

Presents an algorithm for Permutation Routing on a reconfigurable mesh based on the divide and conquer paradigm. the algorithm has a worst case running time of 4n+O(log2/sup /n) communication steps and requires a maximum queue size of 5. the O(log/sup 2/ n) term is associated with communication of single words which convey information about the distribution of packets. Hence, if the packet length is much larger than a single word, then the constant associated with this term is negligible.< >

关键词： Routing Australia parallel machines Delay distributed computing

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the MasPar scalable Unix I/O system

The MasPar scalable Unix I/O system

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International symposium on parallel processing

作者： J.R. Nickolls MasPar Computer Corporation Sunnyvale CA USA

Scalable parallel computers require I/O balanced with computational power to solve data-intensive problems. distributed memory architectures call for I/O hardware and software beyond those of conventional scalar systems. this paper introduces the MasPar I/O system, designed to provide balanced and scalable data-parallel Unix I/O. the architecture and implementation of the I/O hardware and software are described. Key elements include parallel access to conventional Unix file descriptors and a self-routing multistage network coupled with a buffer memory for flexible parallel I/O transfers. Performance measurements are presented for parallel Unix I/O with a scalable RAID disk array, a RAM disk, and a HIPPI interconnect.< >

关键词： Concurrent computing Computer architecture parallel processing Hardware Application software Memory architecture parallel programming Communication system control Reduced instruction set computing Process control

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the block distributed memory model for shared memory multiprocessors

The block distributed memory model for shared memory multipr...

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International symposium on parallel processing

作者： J. JaJa Kwan Woo Ryu Department of Electrical Engineering Institute for Advanced Computer Studies Institute for Systems Research University of Maryland College Park MD USA Departrnent of Computer Engineering Kyungpook National University South Korea Institute for Systems Research University of Maryland College Park MD USA

Introduces a computation model for developing and analyzing parallel algorithms on distributed memory machines. the model allows the design of algorithms using a single address space and does not assume any particular interconnection topology. We capture performance by incorporating a cost measure for interprocessor communication induced by remote memory accesses. the cost measure includes parameters reflecting memory latency, communication bandwidth, and spatial locality. Our model allows the initial placement of the input data and pipelined prefetching. We use our model to develop parallel algorithms for various data rearrangement problems, load balancing, sorting, FFT, and matrix multiplication. We show that most of these algorithms achieve optimal or near optimal communication complexity while simultaneously guaranteeing an optimal speed-up in computational complexity.< >

关键词： Algorithm design and analysis parallel algorithms Costs Concurrent computing distributed computing Computational modeling Topology Delay Bandwidth Prefetching

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All-to-all communication on meshes with wormhole routing

All-to-all communication on meshes with wormhole routing

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International symposium on parallel processing

作者： R. thakur A. Choudhary Northeast Parallel Architectures Center Syracuse University Syracuse NY USA

Describes several algorithms to perform all-to-all communication on a two-dimensional mesh connected computer with wormhole routing. the authors discuss both direct algorithms, in which data is sent directly from source to destination processor, and indirect algorithms in which data is sent through one or more intermediate processors. the authors propose algorithms for both power-of-two and non power-of-two meshes as well as an algorithm which works for any arbitrary mesh. they have developed analytical models to estimate the performance of the algorithms on the basis of system parameters. Performance results obtained on the Intel Touchstone Delta are compared with the estimated values.< >

关键词： Routing Concurrent computing Analytical models Delay parallel architectures Educational institutions Computer networks distributed computing Etching Application software

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Fair Down to the Device: A GC-Aware Fair Scheduler for SSD 8

Fair Down to the Device: A GC-Aware Fair Scheduler for SSD

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8th ieee Non-Volatile Memory Systems and Applications symposium (NVMSA)

作者： Ji, Cheng Wang, Lun Li, Qiao Gao, Congming Shi, Liang Yang, Chia-Lin Xue, Chun Jason City Univ Hong Kong Dept Comp Sci Hong Kong Peoples R China Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan Chongqing Univ Coll Comp Sci Chongqing Peoples R China East China Normal Univ Sch Comp Sci & Software Engn Shanghai Peoples R China

ISBN: (纸本)9781728138541

Solid-state drives (SSD) are the mainstream solutions for massive data storage today. For modern computer systems, fair resource assignment is a critical design consideration and has drawn great interests in recent years. Although there are several I/O fairness schedulers proposed on the host side for SSDs, process fairness could still be dramatically degraded if garbage collection (GC) is triggered in the device side. A GC operation could block I/O requests, which causes unpredictable read/write latency variation and further impacts fairness between processes. this paper proposes Fair-GC, a novel coordinated host and device I/O scheduling strategy to achieve true fairness considering GC interferences. the key idea is to orchestrate GC operations inside SSDs carefully such that performance of a process is penalized by GC in the same degree (or comparable) as when it runs alone. In this way, the I/O fairness maintained by the host-side scheduler can be maintained in the presence of GC. Furthermore, our scheduler ensures that the timeslice of a process maintained at the host-side scheduler is updated in a timely manner to avoid unnecessary slowdown for maintaining fairness. Experimental results with a wide range of workloads verify that the proposed technique can achieve fairness as well as improve the throughput significantly. Compared to conventional fairness-based I/O scheduler, Fair-GC can reduce the slowdown of real applications by up to 99%, and improve the throughput by as much as 225%, respectively.

关键词： Performance evaluation Computer science throughput Flash memories parallel processing Interference Quality of service

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Projection of the Array-OL specification language onto the Kahn process network computation model

Projection of the Array-OL specification language onto the K...

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International symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： A. Amar P. Boulet P. Dumont Laboratoire dInformatique Fondamentale de Lille Universite des Sciences et de la Technologie de Lille Villeneuve d'Ascq France

the Array-OL specification model has been introduced to model systematic signal processing applications. this model is multidimensional and allows to express the full potential parallelism of an application: both task and data parallelism. the Array-OL language is an expression of data dependences and thus allows many execution orders. In order to execute Array-OL applications on distributed architectures, we show here how to project such specification onto the Kahn process network model of computation. We show how Array-OL code transformations allow to choose a projection adapted to the target architecture.

关键词： Specification languages Computer networks Computational modeling parallel processing Computer architecture Array signal processing Multidimensional signal processing Multidimensional systems distributed computing Adaptive arrays

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CoCache: Multi-layer Multi-path Cooperative Cache Accelerating the Deployment of Large Scale Virtual Machines

CoCache: Multi-layer Multi-path Cooperative Cache Accelerati...

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2014 ieee 8th International symposium on Service Oriented System Engineering

作者： Ziyang Li Zhaoning Zhang Huiba Li Yuxing Peng National Key Laboratory for Parallel and Distributed Processing National University of Defense Technology China

By analyzing the problems and challenges of virtual machine image store system in cloud computing environment, we present a cooperative persistent cache (CoCache) for virtual disks. CoCache takes advantage of the service ability of the cached nodes by providing virtual image data service for other nodes. CoCache can transfer data between nodes in a P2P pattern, for extending data service ability of the system. CoCache is realized in the kernel space of Linux, can support any kind of VMM. Experiments show that CoCache can effectively reduce the cost during virtual machines read data, and promote the service ability of virtual machine storage system. Layer-aware cache policy is proposed specially for improving cache hit rate in the multi-layer and multipath environment.

关键词： Virtual machining Servers Image storage Cloud computing Computer architecture System performance Cache storage

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Proceedings - Eighth International symposium on Autonomous Decentralized Systems ISADS 2007

Proceedings - Eighth International Symposium on Autonomous D...

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8th International symposium on Autonomous Decentralized Systems, ISADS 2007

ISBN: (纸本)076952804X

the proceedings contain 69 papers. the topics discussed include: towards distributed Web service composition;Collaboration policy generation in dynamic collaborative SOA;ontology-based test case generation for testing Web services;global constraint checking at run-time;the semantic data space for loosely coupled service provisioning;mobility support for users in wireless sensor networks;change management in semantic business processes modeling;an on-demand address allocation scheme for query based sensor networks;optimizing query injection from mobile objects to sensor networks;autonomous decentralized load tracking systems and evaluation criteria for response and stability;virtual device composition;trust for vehicular applications;dynamic clustering model for high service availability;an approach to positioning road-users in a telematics network;self-organizing pervasive online communities;and preventing resource exhaustion attacks in ad hoc networks.

关键词： Web services

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parallel routing of VLSI circuits based on net independency

Parallel routing of VLSI circuits based on net independency

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International symposium on parallel processing

作者： H. Spruth F. Johannes Institute of Electronic Design Automation Technical University Munich Munich Germany

During the layout synthesis of integrated circuits, a major part of the time is spent with routing the interconnections of the chip's cells. Even for the most simple optimization criteria, this problem is np-complete, making the use of heuristics necessary. But even when using heuristics, the time required by the routing phase is very high. In the past, several approaches have been proposed to speed up the routing phase by applying parallel processing. Most of these approaches distribute the routing area among processors and have to cope with a considerable communication overhead. In this paper, we present a novel approach where sets of nets are distributed. We show experimentally that this approach leads to significant speedups even in workstation networks.< >

关键词： Routing Very large scale integration Workstations Integrated circuit synthesis Integrated circuit interconnections Pins Partitioning algorithms Electronic design automation and methodology Integrated circuit layout Network synthesis

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