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the block distributed memory model for shared memory multiprocessors

The block distributed memory model for shared memory multipr...

引用

International symposium on parallel processing

作者： J. JaJa Kwan Woo Ryu Department of Electrical Engineering Institute for Advanced Computer Studies Institute for Systems Research University of Maryland College Park MD USA Departrnent of Computer Engineering Kyungpook National University South Korea Institute for Systems Research University of Maryland College Park MD USA

Introduces a computation model for developing and analyzing parallel algorithms on distributed memory machines. the model allows the design of algorithms using a single address space and does not assume any particular interconnection topology. We capture performance by incorporating a cost measure for interprocessor communication induced by remote memory accesses. the cost measure includes parameters reflecting memory latency, communication bandwidth, and spatial locality. Our model allows the initial placement of the input data and pipelined prefetching. We use our model to develop parallel algorithms for various data rearrangement problems, load balancing, sorting, FFT, and matrix multiplication. We show that most of these algorithms achieve optimal or near optimal communication complexity while simultaneously guaranteeing an optimal speed-up in computational complexity.< >

关键词： Algorithm design and analysis parallel algorithms Costs Concurrent computing distributed computing Computational modeling Topology Delay Bandwidth Prefetching

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parallel bidirectional heuristic search with dynamic process re-direction

Parallel bidirectional heuristic search with dynamic process...

引用

International symposium on parallel processing

作者： A.A. Toptsis Department of Computer Science and Mathematics Atkinson College York University Toronto ONT Canada

Non-wave shaping parallel bidirectional heuristic search algorithms have been reported to suffer of the bidirectional search anomaly. Although wave-shaping is considered as the most natural approach, parallel bidirectional wave-shaping algorithms are extremely scarce. We introduce a wave-shaping algorithm for parallel bidirectional heuristic search in distributed memory environments. the method is inspired by the celebrated uniprocessor bidirectional wave-shaping algorithm of DeChampeaux-Sint (1977). Our performance evaluation shows that the proposed method scales well, maintains good performance for increasing problem sizes, and attains close to linear speedup over the sequential DeChampeaux-Sint algorithm.< >

关键词： Artificial intelligence Joining processes Heuristic algorithms Costs Computer science Mathematics Educational institutions parallel processing

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Processor mapping techniques toward efficient data redistribution

Processor mapping techniques toward efficient data redistrib...

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International symposium on parallel processing

作者： E.T. Kalns L.M. Ni Department of Computer Science Michigan State University East Lansing MI USA

Run-time data redistribution can affect algorithm performance in distributed-memory machines. Redistribution of data can be performed between algorithm phases when a different data decomposition is expected to deliver increased performance for a subsequent phase of computation. Additionally, data redistribution can occur at subprogram boundaries. Redistribution, however, represents increased program overhead as algorithm computation is necessarily discontinued while data are exchanged among processor memories. In this paper, we present a technique for data-processor mapping, applicable to data redistribution, that minimizes the total amount of data that must be communicated among processors. the mapping technique is architecture-independent and represents our initial work toward achieving efficient redistribution in distributed-memory machines.< >

关键词： Runtime distributed computing Computer science System performance US Department of Energy High level languages Memory Costs

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Deterministic permutation routing on a reconfigurable mesh

Deterministic permutation routing on a reconfigurable mesh

引用

International symposium on parallel processing

作者： A. Kapoor H. Schroder B. Beresford-Smith Department of E & C Engg. University of Newcastle Callaghan NSW Australia Department of CS University of Newcastle Callaghan NSW Australia

Presents an algorithm for Permutation Routing on a reconfigurable mesh based on the divide and conquer paradigm. the algorithm has a worst case running time of 4n+O(log2/sup /n) communication steps and requires a maximum queue size of 5. the O(log/sup 2/ n) term is associated with communication of single words which convey information about the distribution of packets. Hence, if the packet length is much larger than a single word, then the constant associated with this term is negligible.< >

关键词： Routing Australia parallel machines Delay distributed computing

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the MasPar scalable Unix I/O system

The MasPar scalable Unix I/O system

引用

International symposium on parallel processing

作者： J.R. Nickolls MasPar Computer Corporation Sunnyvale CA USA

Scalable parallel computers require I/O balanced with computational power to solve data-intensive problems. distributed memory architectures call for I/O hardware and software beyond those of conventional scalar systems. this paper introduces the MasPar I/O system, designed to provide balanced and scalable data-parallel Unix I/O. the architecture and implementation of the I/O hardware and software are described. Key elements include parallel access to conventional Unix file descriptors and a self-routing multistage network coupled with a buffer memory for flexible parallel I/O transfers. Performance measurements are presented for parallel Unix I/O with a scalable RAID disk array, a RAM disk, and a HIPPI interconnect.< >

关键词： Concurrent computing Computer architecture parallel processing Hardware Application software Memory architecture parallel programming Communication system control Reduced instruction set computing Process control

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All-to-all communication on meshes with wormhole routing

All-to-all communication on meshes with wormhole routing

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International symposium on parallel processing

作者： R. thakur A. Choudhary Northeast Parallel Architectures Center Syracuse University Syracuse NY USA

Describes several algorithms to perform all-to-all communication on a two-dimensional mesh connected computer with wormhole routing. the authors discuss both direct algorithms, in which data is sent directly from source to destination processor, and indirect algorithms in which data is sent through one or more intermediate processors. the authors propose algorithms for both power-of-two and non power-of-two meshes as well as an algorithm which works for any arbitrary mesh. they have developed analytical models to estimate the performance of the algorithms on the basis of system parameters. Performance results obtained on the Intel Touchstone Delta are compared with the estimated values.< >

关键词： Routing Concurrent computing Analytical models Delay parallel architectures Educational institutions Computer networks distributed computing Etching Application software

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On random sampling for parallel simulated annealing

On random sampling for parallel simulated annealing

引用

International symposium on parallel processing

作者： K.A. Hue W.K. Lee S.D. Lang Dept. of Comput. Sci. Univ. of Central Florida Orlando FL USA Department of Computer Science University of Central Florida Orlando FL USA

We investigate the parallelism of simulated annealing for graph partitioning. A random sampling technique, in which disjoint partitions of the graph are distributed across the processors so that moves can be proposed and evaluated asynchronously in distinct processors, is proposed. Synchronizations among processors are not necessary until the equilibrium is reached at each processor. Such an approach may thus achieve a speedup that is approximately linear in the number of processors. Furthermore, since no interacting moves can occur in our strategy, it is obvious that our scheme is free of errors in cost evaluation.< >

关键词： Sampling methods Simulated annealing Cost function parallel processing Computational modeling Concurrent computing Very large scale integration Computer science Ear Memory architecture

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Improving parallel program execution time with message consolidation

Improving parallel program execution time with message conso...

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International symposium on parallel processing

作者： S. Shafer K. Ghose Loral Federal Systems Owego NY USA Department of Computer Science State University of New York Binghamton NY USA

Introduces a technique for optimizing interprocessor communication in programs for distributed memory multiprocessors. Our basic approach is to combine messages with the explicit goal of reducing the overall execution time, taking into account direct and indirect dependencies among the concurrent units. We first establish that combining messages between a pair of isolated processors is not necessarily useful in reducing the overall execution time of the program because of complex interprocessor dependencies. the conditions under which message combining is profitable are then established. We then search for such conditions along chains of dependencies that exist across several processors and combine messages that satisfy these conditions.< >

关键词： Processor scheduling Routing Optimizing compilers Programming profession Computer science Computer architecture Topology Bandwidth Cost function Delay

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parallel routing of VLSI circuits based on net independency

Parallel routing of VLSI circuits based on net independency

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International symposium on parallel processing

作者： H. Spruth F. Johannes Institute of Electronic Design Automation Technical University Munich Munich Germany

During the layout synthesis of integrated circuits, a major part of the time is spent with routing the interconnections of the chip's cells. Even for the most simple optimization criteria, this problem is np-complete, making the use of heuristics necessary. But even when using heuristics, the time required by the routing phase is very high. In the past, several approaches have been proposed to speed up the routing phase by applying parallel processing. Most of these approaches distribute the routing area among processors and have to cope with a considerable communication overhead. In this paper, we present a novel approach where sets of nets are distributed. We show experimentally that this approach leads to significant speedups even in workstation networks.< >

关键词： Routing Very large scale integration Workstations Integrated circuit synthesis Integrated circuit interconnections Pins Partitioning algorithms Electronic design automation and methodology Integrated circuit layout Network synthesis

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A clustered reduced communication element by element preconditioned conjugate gradient algorithm for finite element computations

A clustered reduced communication element by element precond...

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International symposium on parallel processing

作者： A. Amin P. Sadayappan M. Gudavalli UES Incorporated Ohio State Uinversity USA

the clustered element by element preconditioned conjugate gradient (EBE-PCG) method can be effectively used to solve problems with symmetric positive definite matrices such as those arising in ANTARES-3D, a metal forming finite element (FE) simulation package. Efficient parallelization of this application on distributed memory multiple instruction multiple data (MIMD) parallel computers require automatic partitioning of the finite element domain into clusters of elements and solving the compute intensive parts of these clusters concurrently while minimizing inter-processor communication. Such domain decomposition of the FE graph is accomplished by creating an element interaction graph (EIG) and partitioning the EIG into sub-graphs using the Kernighan-Lin partitioning heuristic. In order to minimize the communication overhead during the solution of the linear systems of equations, a clustered reduced communication EBE-PCG formulation is developed and used. Performance measurements for a blade forging are reported.< >

关键词： Finite element methods Computer aided instruction Concurrent computing distributed computing Symmetric matrices Computational modeling Packaging Application software Linear systems Equations

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