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parallel Intelligent computing in Algebraic Problems 15th

Parallel Intelligent Computing in Algebraic Problems

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15th international Scientific conference on parallel Computational Technologies (PCT)

作者： Il'in, Valery Novosibirsk State Univ Inst Computat Math & Math Geophys SB RAS Novosibirsk Russia

ISBN: (纸本)9783030816919;9783030816902

We consider the issues associated with the creation of an intelligent computing environment for the high-performance solution of a wide class of large algebraic problems, which makes up the most resource-intensive stage of mathematical modeling. the first area of research is devoted to automating the construction of parallel algorithms and their mapping onto supercomputer architecture by investigating the problem of classification and identification of matrix statements and selecting algorithms for specific situations relying on optimization methods. the second aspect is related to the creation of intelligent interfaces, both for internal inter-module interactions and for end-users from various professional backgrounds. the rich functionality of the high-tech software under discussion requires an advanced system content to manage machine experiments. the scale of this development puts on the agenda the creation of an integrated tool environment or ecosystem, as well as the concept of a mathematical knowledge base.

关键词： Algebraic problems Large sparse matrices Classification and identification of statements Selection of optimal parallel algorithms Intelligent computing environment

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A Column-parallel Time-Interleaved SAR/SS ADC for computing in Memory with 2-8bit Reconfigurable Resolution

A Column-Parallel Time-Interleaved SAR/SS ADC for Computing ...

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IEEE international conference on Artificial Intelligence Circuits and Systems (AICAS)

作者： Yuandong Li Li Du Yuan Du Nanjing University Nanjing China

computing in Memory (CiM), as a computing system with non-von Neumann architecture, has been reported as one of the most promising neural network accelerators in the future. Compared with digital-based computation, CiM uses RAM arrays to calculate and store in the analog domain, avoiding the high delay and energy consumption caused by data transfer. However, the computational results require data converters for quantization, which often limits the development of high-performance CiMs. In this work, we propose a 2-8bit reconfigurable time-interleaved hybrid ADC architecture for high-speed CiMs, including successive approximation and single-slope stages. Reconfigurability introduces a trade-off between resolution and conversion speed for ADCs in different computing scenarios. A prototype was implemented in a 55 nm CMOS technology, which occupies an area of 330μm × 13μm and consumes a power of 1.429mW at 8-bit conversion mode. With a Nyquist frequency input sampled at 350 MS/s, the SNDR and SFDR are 40.93 dB and 51.08 dB, respectively. the resultant Walden figure of merit is 44.8 fJ/conv.

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Connectivity and Routing Algorithm of the Data Center network HSDC 17th

Connectivity and Routing Algorithm of the Data Center Networ...

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17th ifip WG 10.3 international conference on network and parallel computing, NPC 2020

作者： Dong, Hui Fan, Jianxi Cheng, Baolei Wang, Yan Zhou, Jingya School of Computer Science and Technology Soochow University Suzhou215006 China

ISBN: (纸本)9783030794774

In order to satisfy the rapidly increasing demand for data volume, large data center networks (DCNs) have been proposed. In 2019, Zhang et al. proposed a new highly scalable DCN architecture named HSDC, which can achieve greater incremental scalability. In this paper, we give the definition of the logical graph of HSDC, named Hn, which can be treated as a compound graph of hypercube and complete graph of the same dimension. First, we prove that the connectivity and tightly super connectivity of Hn are both n. then, we give an O(n) routing algorithm to find a shortest path between any two distinct nodes in Hn, and prove the correctness of this algorithm. In fact, we also prove that the distance constructed by this algorithm is no more than 2 d+ 1 if dn is 2n. © 2021, ifip international Federation for Information Processing.

关键词： Routing algorithms

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A Dynamic Mapping Model for General CNN Accelerator Based on FPGA 17th

A Dynamic Mapping Model for General CNN Accelerator Based on...

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17th ifip WG 10.3 international conference on network and parallel computing, NPC 2020

作者： Zhao, Xiaoqiang Jiang, Jingfei Han, Zhe Xu, Jinwei Liu, Zhiqiang National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China Artificial Intelligence Research Center National Innovation Institute of Defense Technology Beijing China

ISBN: (纸本)9783030794774

As the application scenarios of convolutional neural network (CNN) become more and more complex, the general CNN accelerator based on matrix multiplication has become a new research focus. the existing mapping methods for converting convolution calculation into matrix multiplication need to be improved. this paper proposes a new dynamic mapping model to improve the flexibility and versatility of matrix multiplication. the dynamic mapping model implements two algorithms: dynamic residue processing mapping algorithm (DRPMA) and dilated convolution mapping algorithm (DCMA). the former can dynamically adjust the mapping method according to the number of output channels of the convolution layer, improve the utilization of the multiply-accumulate (MAC) array. the latter extends the efficient support for Dilated CNNs. For demonstration, we implement an accelerator with Verilog on Xilinx VC709 FPGA board and test some typical CNN models. Experimental results show that the general accelerator achieves high performance and energy efficiency. © 2021, ifip international Federation for Information Processing.

关键词： Field programmable gate arrays (FPGA)

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Google Neural network Models for Edge Devices: Analyzing and Mitigating Machine Learning Inference Bottlenecks 21

Google Neural Network Models for Edge Devices: Analyzing and...

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Proceedings of the 30th international conference on parallel Architectures and Compilation Techniques

作者： Amirali Boroumand Saugata Ghose Berkin Akin Ravi Narayanaswami Geraldo F. Oliveira Xiaoyu Ma Eric Shiu Onur Mutlu Carnegie Mellon Univ. and Stanford Univ. Univ. of Illinois Urbana-Champaign Google ETH Zürich Carnegie Mellon Univ. and ETH Zürich

ISBN: (纸本)9781665442787

Emerging edge computing platforms often contain machine learning (ML) accelerators that can accelerate inference for a wide range of neural network (NN) models. these models are designed to fit within the limited area and energy constraints of the edge computing platforms, each targeting various applications (e.g., face detection, speech recognition, translation, image captioning, video analytics). To understand how edge ML accelerators perform, we characterize the performance of a commercial Google Edge TPU, using 24 Google edge NN models (which span a wide range of NN model types) and analyzing each NN layer within each model. We find that the Edge TPU suffers from three major shortcomings: (1) it operates significantly below peak computational throughput, (2) it operates significantly below its theoretical energy efficiency, and (3) its memory system is a large energy and performance bottleneck. Our characterization reveals that the one-size-fits-all, monolithic design of the Edge TPU ignores the high degree of heterogeneity both across different NN models and across different NN layers within the same NN model, leading to the shortcomings we *** propose a new acceleration framework called Mensa. Mensa incorporates multiple heterogeneous edge ML accelerators (including both on-chip and near-data accelerators), each of which caters to the characteristics of a particular subset of NN models and layers. During NN inference, for each NN layer, Mensa decides which accelerator to schedule the layer on, taking into account both the optimality of each accelerator for the layer and layer-to-layer communication costs. Our comprehensive analysis of the Google edge NN models shows that all of the layers naturally group into a small number of clusters, which allows us to design an efficient implementation of Mensa for these models with only three specialized accelerators. Averaged across all 24 Google edge NN models, Mensa improves energy efficiency and throughput by 3

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Evaluating Urban network Activity Hotspots through Granular Cluster Analysis of Spatio-Temporal Data 17

Evaluating Urban Network Activity Hotspots through Granular ...

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17th international conference on network and Service Management (CNSM) - Smart Management for Future networks and Services

作者： Pajo, Jane Frances Kousiouris, George Kyriazis, Dimosthenis Bruschi, Roberto Davoli, Franco Telenor Res Next Generat Technol Fornebu Norway Harokopio Univ Athens Dept Informat & Telemat Athens Greece Univ Piraeus Dept Digital Syst Piraeus Greece Univ Genoa CNIT S2N Natl Lab DITEN Genoa Italy

ISBN: (纸本)9783903176362

Multi-access Edge computing (MEC) is expected to play an essential role in enabling 5G (and beyond) technologies and services. this has driven numerous micro-datacenter (mu DC) deployment studies in the literature, with a common goal of addressing the optimal mu DC placement and dimensioning problems. Along this line, this paper aims at clustering subareas with similar network activity dynamics, to find a good hotspots' representation over the urban area. Leveraging common Machine Learning (ML) and statistics principles, the main contribution of this paper is two-fold: (i) the definition and selection of dynamicity features based on real telecommunications datasets;and (ii) the granular cluster evaluation and analysis based on agglomerative hierarchical clustering. three feature sets (containing 20, 12 and 8 features, respectively) are evaluated at varying precision levels, showing interesting trends on the number of clusters, heatmaps and intra-cluster correlation. these could potentially provide some valuable indications on the placement and dimensioning of the mu ***-access Edge computing (MEC) is expected to play an essential role in enabling 5G (and beyond) technologies and services. this has driven numerous micro-datacenter (mu DC) deployment studies in the literature, with a common goal of addressing the optimal mu DC placement and dimensioning problems. Along this line, this paper aims at clustering subareas with similar network activity dynamics, to find a good hotspots' representation over the urban area. Leveraging common Machine Learning (ML) and statistics principles, the main contribution of this paper is two-fold: (i) the definition and selection of dynamicity features based on real telecommunications datasets;and (ii) the granular cluster evaluation and analysis based on agglomerative hierarchical clustering. three feature sets (containing 20, 12 and 8 features, respectively) are evaluated at varying precision levels, showing interesting trends

关键词： Feature selection Hierarchical clustering MEC deployment network activity hotspots

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Hybrid parallel Inference for Large Model on Heterogeneous Clusters for High throughput

Hybrid Parallel Inference for Large Model on Heterogeneous C...

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international conference on parallel and Distributed Systems (ICPADS)

作者： Chaonong Xu Weiming Kong Min Liu Mingming Zhang Chao Li Luqi Gong Beijing Key Lab of Petroleum Data Mining China University of Petroleum (Beijing) Beijing China Institute of Intelligent Computing Zhejiang Lab Hangzhou China School of Computer Science (National Pilot Software Engineering School) BUPT Beijing China

In high-throughput intelligent computing scenarios, multi-device parallelism strategies based on data parallelism or pipeline parallelism have been extensively utilized to accelerate large deep neural network model inference. Data parallelism offers nearly linear improvement in inference speed, but it is limited by the memory capacity of a single device which constrains the model size. On the other hand, pipeline parallelism can support larger models, but the total communication of the activations among devices is high, which limits the improvement of the inference speed. To address the demand for efficient model inference in high-throughput heterogeneous scenarios, we proposes a hybrid parallelism strategy that combines data parallelism and pipeline parallelism. the strategy involves grouping heterogeneous device clusters and then employing inter-group data parallelism along with intra-group pipeline parallelism. Moreover, we propose an algorithm to find an optimal hybrid parallel inference strategy with maximum throughput. the control variables of the strategy includes the number of groups, group-device assignments and model partition ratios. Our experimental evaluation demonstrates that compared to PipeEdge, a pipeline parallel inference framework for heterogeneous cluster, our strategy can achieve 1.7× −3.4× acceleration in an 8-device heterogeneous cluster without loss of accuracy.

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SODA: A Semantics-Aware Optimization Framework for Data-Intensive Applications Using Hybrid Program Analysis 14

SODA: A Semantics-Aware Optimization Framework for Data-Inte...

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IEEE 14th international conference on Cloud computing (CLOUD)

作者： Rao, Bingbing Liu, Zixia Zhang, Hong Lu, Siyang Wang, Liqiang Univ Cent Florida Dept Comp Sci Orlando FL 32816 USA Hebei Univ Sch Cyber Secur & Comp Baoding Heibei Peoples R China Beijing Jiaotong Univ Sch Comp & Informat Technol Beijing Peoples R China

ISBN: (纸本)9781665400602

In the era of data explosion, a growing number of data-intensive computing frameworks, such as Apache Hadoop and Spark, have been proposed to handle the massive volume of unstructured data in parallel. Since programming models provided by these frameworks allow users to specify complex and diversified user-defined functions (UDFs) with predefined operations, the grand challenge of tuning up entire system performance arises if programmers do not fully understand the semantics of code, data, and runtime systems. In this paper, we design a holistic semantics-aware optimization for data-intensive applications using hybrid program analysis (SODA) to assist programmers to tune performance issues. SODA is a two-phase framework: the offline phase is a static analysis that analyzes code and performance profiling data from the online phase of prior executions to generate a parameterized and instrumented application;the online phase is a dynamic analysis that keeps track of the application's execution and collects runtime information of data and system. Extensive experimental results on lour realworld Spark applications show that SODA can gain up to 60%, 10%, 8%, faster than its original implementation, with the three proposed optimization strategies, i.e., cache management, operation reordering, and element pruning, respectively.

关键词： Data-Intensive computing program analysis semantics-aware cache management

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TianheQueries: Ultra-Fast and Scalable Graph Queries on Tianhe Supercomputer

TianheQueries: Ultra-Fast and Scalable Graph Queries on Tian...

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IEEE international conference on High Performance computing and Communications (HPCC)

作者： Xinbiao Gan Guang Wu Cong Liu Jiaqi Si Xuguang Chen Bo Yang Tiejun Li National University of Defense technology Information center of Logistic Support Department CMC

As graph-based services have been widespreadly integrated into daily lives, extremely-fast and scalable graph queries are receiving increasing attention. Graph querying al-gorithms including BFS(Breadth First Search) and SSSP(Single Source Shortest Path) are promising engines for graph-based applications. Unfortunately, current graph queries often deliver low efficiency owing to sequential execution and poor scalability. this paper presents TianheQueries: an ultra-fast and scalable graph querying engine on Tianhe supercomputer. TianheQueries proposes an efficient hardware prefetching and caching mechanism that can pipeline vertices gather, traversal and vertices scatter so as to accelerate graph queries with the utilization of pipeline parallelism. and (ii) presents a topology-aware communication aggregation for inter-domain messages more than from the same source node by leveraging the network topology information to perform more aggressively messages aggregation. We use both benchmark and real-world graphs to demonstrate the effectiveness of TianheQueries. Specially, TianheQueries helps Tianhe Exa-node win the top spot of the latest Green-Graph500 lists both big data and small data categories. Further-more, TianheQueries-based SSSP tests on Tianhe supercomputer is superior to the fastest SSSP systems in the latest Graph500 lists.

关键词： network topology Prefetching Pipelines parallel processing Big Data Benchmark testing Supercomputers

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Enhanced Multi-Bit Computation Using CIM SRAM Technology

Enhanced Multi-Bit Computation Using CIM SRAM Technology

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international conference on Solid-State and Integrated Circuit Technology

作者： Ruiyong Zhao Yibo Hu Zhipeng Ren Yizhe Yin Jing Chen Shanghai Institute of Microsystem and Information Technology Chinese Academy of Sciences Shanghai China

ISBN: (数字)9798350361834

ISBN: (纸本)9798350361841

Tackling the challenges of substantial data loading latency and excessive computational circuit area overhead prevalent in contemporary multi-bit Compute-In-Memory (CIM) SRAM macro designs, this paper introduces a strategy based on “complementary cell computation architectures coupled with complementary data inputs.” this approach establishes a high-bandwidth, high-compute-performance, and expansible multi-bit CIM SRAM macro, particularly apt for the highly parallel matrix multiplication operations encountered in neural network algorithms. the proposed CIM SRAM macro unit executes efficient binary multiplications up to 8 bits width without reliance on additional circuits such as ADC or incurring data loading delays, thereby reinforcing computational precision and system bandwidth. Simulation outcomes illustrate that, when operated at a frequency of 1GHz, the HSBC SRAM achieves an area efficiency uplift to $\mathbf{0. 556 {MB}/{mm}^th}$ and $\mathbf{{186TOPS/mm}^th}$ by expanding both input and weight data widths to 8 bits.

关键词： Integrated circuit technology Microprocessors Loading Neural networks Random access memory Computer architecture In-memory computing Common Information Model (computing) Delays Computational efficiency

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