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11th international conference on Contemporary computing (IC3)

作者： Kumar, Anil Talawar, Basavaraj Natl Inst Technol Karnataka Dept Comp Sci & Engn SPARK Lab Mangalore India

ISBN: (纸本)9781538668351

Chip Multiprocessors(CMPs) and Multiprocessor System-on-Chips(MPSoCs) are meeting the ever increasing demand for high performance in processing large scale data and applications. there is a corresponding increase in the volume and frequency of traffic in the network-on-Chip(NoC) architectures like CMPs and SoCs. NoC performance parameters like network latency, flit latency and hop count are critical measures which directly influence the overall performance of the architecture and execution time of the application. Unfortunately, cycle-accurate software simulators become slow for interactive use with an increase in architectural size of NoC. In order to provide the chip designer with an efficient framework for accurate measurements of NoC performance parameters, we propose a Machine Learning(ML) framework. Which is designed using different ML regression algorithms like Support Vector Regression(SVR) with different kernels and Artificial Neural networks(ANN) with different activation functions. the proposed learning framework can be used to analyze the performance parameters of Mesh and Torus based NoC architectures. Results obtained are compared against the widely used cycle-accurate Booksim simulator. Experiments were conducted by variables like topology size from 2x2 to 30x30 with different virtual channels, traffic patterns and injection rates. the framework showed an approximate prediction error of 5% to 8% and overall minimum speedup of 1500x to 2000x.

关键词： network-on-Chip Machine Learning Support Vector Regression Booksim Artificial Neural network Latency Hop Count

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A Portable, Automatic Data Quantizer for Deep Neural networks 27

A Portable, Automatic Data Quantizer for Deep Neural Network...

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27th IEEE/ACM/ifip international conference on parallel Architectures and Compilation Techniques (PACT)

作者： Oh, Young H. Quan, Quan Kim, Daeyeon Kim, Seonghak Heo, Jun Jung, Sungjun Jang, Jaeyoung Lee, Jae W. Sungkyunkwan Univ Dept Elect & Comp Engn Suwon South Korea Seoul Natl Univ NPRC Dept Comp Sci & Engn Seoul South Korea

ISBN: (纸本)9781450359863

With the proliferation of AI-based applications and services, there are strong demands for efficient processing of deep neural networks (DNNs). DNNs are known to be both compute- and memory-intensive as they require a tremendous amount of computation and large memory space. Quantization is a popular technique to boost efficiency of DNNs by representing a number with fewer bits, hence reducing both computational strength and memory footprint. However, it is a difficult task to find an optimal number representation for a DNN due to a combinatorial explosion in feasible number representations with varying bit widths, which is only exacerbated by layer-wise optimization. Besides, existing quantization techniques often target a specific DNN framework and/or hardware platform, lacking portability across various execution environments. To address this, we propose libnumber, a portable, automatic quantization framework for DNNs. By introducing Number abstract data type (ADT), libnumber encapsulates the internal representation of a number from the user. then the auto-tuner of libnumber finds a compact representation (type, bit width, and bias) for the number that minimizes the user-supplied objective function, while satisfying the accuracy constraint. thus, libnumber effectively separates the concern of developing an effective DNN model from low-level optimization of number representation. Our evaluation using eleven DNN models on two DNN frameworks targeting an FPGA platform demonstrates over 8x (7x) reduction in the parameter size on average when up to 7% (1%) loss of relative accuracy is tolerable, with a maximum reduction of 16x, compared to the baseline using 32-bit floating-point numbers. this leads to an geomean speedup of 3.79x with a maximum speedup of 12.77x over the baseline, while requiring only minimal programmer effort.

关键词： Auto-tuning Deep neural networks Quantization Optimzation Performance Approximate computing

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GRAM: A GPU-based property graph traversal and query for HPC rich metadata management 1

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15th ifip international conference on network and parallel computing, NPC 2018

作者： Li, Wenke Shi, Xuanhua Huang, Hong Zhao, Peng Jin, Hai Dai, Dong Chen, Yong Services Computing Technology and System Lab Big Data Technology and System Lab Huazhong University of Science and Technology Wuhan430074 China Department of Computer Science Texas Tech University LubbockTX43104 United States

ISBN: (数字)9783030056773

ISBN: (纸本)9783030056766

In HPC systems, rich metadata are defined to describe rich information about data files, like the executions that lead to the data files, the environment variables, and the parameters of all executions, etc. Recent studies have shown the feasibility of using property graph to model rich metadata and utilizing graph traversal to query rich metadata stored in the property graph. We propose to utilize GPU to process the rich metadata graphs. there are generally two challenges to utilize GPU for metadata graph query. First, there is no proper data representation for the metadata graph on GPU yet. Second, there is no optimization techniques specifically for metadata graph traversal on GPU neither. In order to tackle these challenges, we propose GRAM, a GPU-based property graph traversal and query framework. GRAM uses GPU to express metadata graph in Compressed Sparse Row (CSR) format, and uses Structure of Arrays (SoA) layout to store properties. In addition, we propose two new optimizations, parallel filtering and basic operations merging, to accelerate the metadata graph traversal. Our evaluation results show that GRAM can be effectively applied to user scenarios in HPC systems, and the performance of metadata management is greatly improved. © ifip international Federation for Information Processing 2018.

关键词： Metadata

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StrieGD: A sampling trie indexed compression algorithm for large-scale gene data 1

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15th ifip international conference on network and parallel computing, NPC 2018

作者： Gao, Yanzhen Bao, Xiaozhen Xing, Jing Wei, Zheng Ma, Jie Zhang, Peiheng Institute of Computing Technology Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (数字)9783030056773

ISBN: (纸本)9783030056766

the development of next-generation sequencing (NGS) technology presents a considerable challenge for data storage. To address this challenge, a number of compression algorithms have been developed. However, currently used algorithms fail to simultaneously achieve high compression ratio as well as high compression speed. We propose an algorithm STrieGD that is based on a trie index structure for improving the compression speed of FASTQ files. To reduce the size of the trie index structure, our approach adopts a sampling strategy followed by a filtering step using quality scores. Our experiment shows that the compression ratio of our algorithm increased by approx. 50% over GZip, while being nearly equal to that of DSRC. Importantly, the compression speed of the STrieGD is 3 to 6 times faster than GZip and about 55% faster than DSRC. Moreover, with the increase of compressors, the compression ratio remains stable and the compression speed is nearly linear scalable. © ifip international Federation for Information Processing 2018.

关键词： Data compression

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Properties of the parallel discrete event simulation algorithms on small-world communication networks 8

Properties of the parallel discrete event simulation algorit...

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Selected Papers of the 8th international conference "Distributed computing and Grid-Technologies in Science and Education", GRID 2018

作者： Ziganurova, Liliia Shchur, Lev Science Center in Chernogolovka Chernogolovka Moscow Region142432 Russia National Research University Higher School of Economics Moscow101000 Russia Landau Institute for Theoretical Physics Chernogolovka Moscow Region142432 Russia

Synchronization aspects in the method of large-scale simulation, knovvn as parallel discrete event simulation (PDES), analyzed using the models of the time profile evolutions. Time profile is formed vvith the local virtual times of the processes. Time profile evolution in the simplest cases reminds the growth of the surface in the models of statistical physics. this simplest case considers only local dependences, the message exchange with the nearest neighbors. In the real simulations, the exchange can be with any of the processes, and we can consider the communication network of messages forms the small-world network. We found the enhancement of synchronization with the growing average shortest path of the small-world network. At the same time, the utilization drops down, although on the moderate level. We present the preliminary results of our study. the work is supported by grant 14-21-00158 of the Russian Science Foundation. © 2018 Liliia Ziganurova, Lev Shchur.

关键词： Synchronization

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ALOR: Adaptive layout optimization of raft groups for heterogeneous distributed key-value stores 1

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15th ifip international conference on network and parallel computing, NPC 2018

作者： Wang, Yangyang Chai, Yunpeng Wang, Xin Key Laboratory of Data Engineering and Knowledge Engineering MOE Beijing China School of Information Renmin University of China Beijing China College of Intelligence and Computing Tianjin University Tianjin China

ISBN: (数字)9783030056773

ISBN: (纸本)9783030056766

Many distributed key-value storage systems employ the simple and effective Raft protocol to ensure data consistency. they usually assume a homogeneous node hardware configuration for the underlying cluster and thus adopt even data distribution schemes. However, today’s distributed systems tend to be heterogeneous in nodes’ I/O devices due to the regular worn I/O device replacement and the emergence of expensive new storage media (e.g., non-volatile memory). In this paper, we propose a new data layout scheme called Adaptive Layout Optimization of Raft groups (ALOR), considering the hardware heterogeneity of the cluster. ALOR aims to optimize the data layout of Raft groups to achieve a better practical load balance, which leads to higher performance. ALOR consists of two components: leader migration in Raft groups and skewed data layout based on cold data migration. We conducted experiments on a practical heterogeneous cluster, and the results indicate that, on average, ALOR improves throughput by 36.89%, reduces latency and 99th percentile tail latency by 24.54% and 21.32%, respectively. © ifip international Federation for Information Processing 2018.

关键词： Digital storage

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Always-ON Visual node with a Hardware-Software Event-Based Binarized Neural network Inference Engine 15

Always-ON Visual node with a Hardware-Software Event-Based B...

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15th ACM international conference on computing Frontiers

作者： Rusci, Manuele Rossi, Davide Flamand, Eric Gottardi, Massimo Farella, Elisabetta Benini, Luca Univ Bologna DEI Bologna Italy GreenWaves Technol Villard Bonnot France Fdn Bruno Kessler Trento Italy Swiss Fed Inst Technol D ITET Zurich Switzerland

ISBN: (纸本)9781450357616

this is work introduces an ultra-low-power visual sensor node coupling event-based binary acquisition with Binarized Neural networks (BNNs) to deal with the stringent power requirements of always-on vision systems for IoT applications. By exploiting in-sensor mixed-signal processing, an ultra-low-power imager generates a sparse visual signal of binary spatial-gradient features. the sensor output, packed as a stream of events corresponding to the asserted gradient binary values, is transferred to a 4-core processor when the amount of data detected after frame difference surpasses a given threshold. then, a BNN trained with binary gradients as input runs on the parallel processor if a meaningful activity is detected in a pre-processing stage. During the BNN computation, the proposed Event-based Binarized Neural network model achieves a system energy saving of 17.8% with respect to a baseline system including a low-power RGB imager and a Binarized Neural network, while paying a classification performance drop of only 3% for a real-life 3-classes classification scenario. the energy reduction increases up to 8x when considering a long-term always-on monitoring scenario, thanks to the event-driven behavior of the processing sub-system.

关键词： always-on vision system event-based sensing binarized neural network ultra-low power visual sensing

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Distributed manufacturing resource selection strategy in cloud manufacturing

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international JOURNAL OF ADVANCED MANUFACTURING TECHNOLOGY 2018年第9-12期94卷 3375-3388页

作者： Wang, Lei Guo, Shunsheng Li, Xixing Du, Baigang Xu, Wenxiang Wuhan Univ Technol Sch Mech & Elect Engn Wuhan 430070 Peoples R China

With the development of the information technology and logistics industry, industrial production models are more likely to be innovated than ever before. therefore, there is a tendency for a large number of manufacturing enterprises to start outsourcing their manufacturing activities to more professional subcontractors so they could pay more attention to their core business. Cloud manufacturing (CMfg), as a supplement to cloud computing and big data, is also a new network manufacturing mode that is service-oriented. this mode makes it even more complex and impractical to organize and optimize manufacturing resources. Considering this problem, this paper proposes a manufacturing resource selection strategy based on an improved distributed genetic algorithm (DGA) for manufacturing resource combinatorial optimization (MRCO) in CMfg. We divided the DGA into several sections and distributed and optimized the process, which not only guaranteed algorithm speed but also expanded the search range and improved the accuracy. A case study, a performance comparison between a simple genetic algorithm (SGA) and a working procedure priority-based algorithm (WPPBA) is presented later in this paper. Experimental results showed that the proposed method is preferable and a more effective choice for searching for the optimal solution.

关键词： Cloud manufacturing Manufacturing resource combinatorial optimization Distributed genetic algorithm parallel optimization

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Performance Analysis and CPU vs GPU Comparison for Deep Learning 6

Performance Analysis and CPU vs GPU Comparison for Deep Lear...

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6th international conference on Control Engineering and Information Technology (CEIT)

作者： Buber, Ebubekir Diri, Banu Yildiz Tech Univ Comp Engn Dept Istanbul Turkey

ISBN: (纸本)9781538676417

Deep learning approaches are machine learning methods used in many application fields today. Some core mathematical operations performed in deep learning are suitable to be parallelized. parallel processing increases the operating speed. Graphical Processing Units (GPU) are used frequently for parallel processing. parallelization capacities of GPUs are higher than CPUs, because GPUs have far more cores than Central Processing Units (CPUs). In this study, benchmarking tests were performed between CPU and GPU. Tesla k8O GPU and Intel Xeon Gold 6126 CPU was used during tests. A system for classifying Web pages with Recurrent Neural network (RNN) architecture was used to compare performance during testing. CPUs and GPUs running on the cloud were used in the tests because the amount of hardware needed for the tests was high. During the tests, some hyperparameters were adjusted and the performance values were compared between CPU and GPU. It has been observed that the GPU runs faster than the CPU in all tests performed. In some cases, GPU is 4-5 times faster than CPU, according to the tests performed on GPU server and CPU server. these values can be further increased by using a GPU server with more features.

关键词： cloud computing gpu cpu performance analysis deep learning

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P4NFV: An NFV Architecture with Flexible Data Plane Reconfiguration 14

P4NFV: An NFV Architecture with Flexible Data Plane Reconfig...

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14th international conference on network and Service Management, CNSM 2018 and Workshops, 1st international Workshop on High-Precision networks Operations and Control, HiPNet 2018 and 1st Workshop on Segment Routing and Service Function Chaining, SR+SFC 2018

作者： He, Mu Basta, Arsany Blenk, Andreas Deric, Nemanja Kellerer, Wolfgang Department of Communication Networks Technical University of Munich Germany

ISBN: (纸本)9783903176140

Current architecture proposals for network Function Virtualization (NFV) do not integrate hardware-accelerated network function implementations. Recent research studies have shown that pure software-based implementations cannot achieve the needed line rates for todays network services. We propose P4NFV to fill this gap. Making use of an additional abstraction layer, P4NFV is an architecture that can achieve software-based network function implementations as well as handle P4 for programming protocol-independent packet processors. With P4NFV, network operators can still instantiate network functions that are specified in terms of computing and storage hardware, while making use of the performance improvements of P4-enhanced networking hardware. Moreover, in order to take the fast changing nature of todays network services into account, P4NFV integrates mechanisms to reconfigure P4-based network functions at runtime: another missing gap in literature. Based on a proof-of-concept implementation of P4NFV for four network functions, we show promising measurement results. Whereas the network function implementations tailored towards reconfigurations add only marginal overhead, even configuring network functions at runtime does not notably affect network service operations with higher latency or severe packet loss. © 2018 ifip.

关键词： network function virtualization

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