检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,133 篇 会议
24 篇 期刊文献
20 册 图书

馆藏范围

1,177 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

976 篇 工学
- 909 篇 计算机科学与技术...
- 419 篇 软件工程
- 228 篇 信息与通信工程
- 147 篇 电气工程
- 67 篇 电子科学与技术（可...
- 42 篇 控制科学与工程
- 39 篇 生物工程
- 29 篇 机械工程
- 29 篇 动力工程及工程热...
- 24 篇 测绘科学与技术
- 19 篇 生物医学工程（可授...
- 15 篇 安全科学与工程
- 11 篇 光学工程
- 9 篇 建筑学
- 9 篇 网络空间安全
- 8 篇 仪器科学与技术
- 8 篇 材料科学与工程（可...
- 8 篇 化学工程与技术
210 篇 理学
- 138 篇 数学
- 42 篇 生物学
- 35 篇 系统科学
- 34 篇 统计学（可授理学、...
- 19 篇 物理学
133 篇 管理学
- 98 篇 管理科学与工程(可...
- 62 篇 工商管理
- 43 篇 图书情报与档案管...
17 篇 经济学
- 17 篇 应用经济学
17 篇 农学
- 15 篇 作物学
14 篇 法学
- 10 篇 社会学
13 篇 医学
- 9 篇 临床医学
2 篇 教育学
2 篇 军事学
1 篇 艺术学

主题

36 篇 cloud computing
33 篇 parallel process...
27 篇 parallel computi...
24 篇 network topology
22 篇 neural networks
19 篇 machine learning
17 篇 deep learning
17 篇 network security
16 篇 grid computing
15 篇 scalability
15 篇 computer archite...
15 篇 cluster computin...
14 篇 parallel program...
14 篇 computational mo...
14 篇 network architec...
14 篇 edge computing
13 篇 mapreduce
13 篇 high performance...
12 篇 monitoring
12 篇 topology

机构

17 篇 university of ch...
14 篇 institute of com...
9 篇 national univers...
6 篇 college of compu...
6 篇 shandong univ in...
5 篇 university of sc...
5 篇 school of comput...
5 篇 services computi...
5 篇 college of intel...
4 篇 college of physi...
4 篇 qingdao univ col...
4 篇 school of comput...
4 篇 univ bologna dei...
4 篇 jilin univ coll ...
4 篇 imperial vision ...
4 篇 institute of com...
3 篇 college of compu...
3 篇 national enginee...
3 篇 tsinghua univers...
3 篇 department of co...

作者

14 篇 jin hai
7 篇 li daxing
6 篇 liu yang
6 篇 dvorsky jiri
6 篇 shi xuanhua
6 篇 hsu ching-hsien
6 篇 vojacek lukas
5 篇 qian depei
5 篇 xiao limin
4 篇 man ka lok
4 篇 liu jie
4 篇 drazdilova pavla
4 篇 rossi davide
4 篇 benini luca
4 篇 tan guangming
4 篇 zhang jie
4 篇 daxing li
4 篇 beferull-lozano ...
4 篇 li wei
4 篇 tong tong

语言

1,170 篇 英文
5 篇 中文
3 篇 其他

检索条件"任意字段=8th IFIP International Conference on Network and Parallel Computing"

共 1177 条记录，以下是381-390 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

HSAStore: A Hierarchical Storage Architecture for computing Systems Containing Large-Scale Intermediate Data 13th

HSAStore: A Hierarchical Storage Architecture for Computing ...

引用

13th European-Alliance-for-Innovation (EAI) international conference on Collaborative computing - networking, Applications and Worksharing (CollaborateCom)

作者： Zhang, Zhoujie Xiao, Limin Su, Shubin Ruan, Li Wei, Bing Zhou, Nan Liu, Xi Wang, Haitao Wei, Zipeng Beihang Univ State Key Lab Software Dev Environm Beijing 100191 Peoples R China Beihang Univ Sch Comp Sci & Engn Beijing 100191 Peoples R China Space Star Technol Co Ltd Beijing 100086 Peoples R China

ISBN: (纸本)9783030009168;9783030009151

this paper introduces HSAStore, a newly designed storage system whose goal goes to build an efficient storage system for computing systems that containing large-scale intermediate data. HSAStore involves three sub-systems to work together, a distributed file system which is in charge of the intermediate data, a centralized network Attached Storage (NAS) which stores the raw input data and the results data, and a local file system that serves for the local data. the HSAStore takes full advantage of the network bandwidth of the computing cluster. Moreover, HSAStore adopts the distributed file system, so it is helpful for efficient execution of parallel programs. Experiments show that HSAStore has a significant improvement on efficiency in the computing systems that containing large-scale intermediate data.

关键词： Hierarchical storage architecture Bandwidth bottleneck Large-scale intermediate data Distributed file system

来源：评论

学校读者我要写书评

暂无评论

High Performance Regular Expression Matching on FPGA 13th

High Performance Regular Expression Matching on FPGA

引用

13th European-Alliance-for-Innovation (EAI) international conference on Collaborative computing - networking, Applications and Worksharing (CollaborateCom)

作者： Yang, Jiajia Jiang, Lei Bai, Xu Dai, Qiong UCAS Inst Informat Engn Sch Cyber Secur Beijing Peoples R China

ISBN: (纸本)9783030009168;9783030009151

Deep Packet Inspection (DPI) technology has been widely deployed in network Intrusion Detection System (NIDS) to detect attacks and viruses. State-of-the-art NIDS uses Deterministic Finite Automata (DFA) to perform regular expression matching for its stable matching speed. However, traditional DFA algorithm's throughput is limited by the input character's width (usually one character per time). In this paper, we present an architecture named parallel-DFA to accelerate regular expression matching by scanning multiple characters per time. Experimental results show that, our architecture can achieve as high as 1200 Gbps (1.17Tbps) rate on current single Field-Programmable Gate Array (FPGA) chip. this makes it a very practical solution for NIDS in 100G Ethernet standard network, which is currently the fastest approved standard of Ethernet. To the best of our knowledge, this is the fastest matching performance architecture on a single FPGA chip. Besides, the throughput is nearly 3 orders of magnitude (916x) than that of original DFA implemented on software. Our architecture is about 183.2x efficiency than that of original DFA.

关键词： Deep Packet Inspection Regular expression matching DFA FPGA network security

来源：评论

学校读者我要写书评

暂无评论

A 65nm 4Kb Algorithm-Dependent computing-in-Memory SRAM Unit-Macro with 2.3ns and 55.8TOPS/W Fully parallel Product-Sum Operation for Binary DNN Edge Processors 65

A 65nm 4Kb Algorithm-Dependent Computing-in-Memory SRAM Unit...

引用

65th IEEE international Solid-State Circuits conference (ISSCC)

作者： Khwa, Win-San Chen, Jia-Jing Li, Jia-Fang Si, Xin Yang, En-Yu Sun, Xiaoyu Liu, Rui Chen, Pai-Yu Li, Qiang Yu, Shimeng Chang, Meng-Fan Natl Tsing Hua Univ Hsinchu Taiwan TSMC Hsinchu Taiwan Univ Elect Sci & Technol China Chengdu Sichuan Peoples R China Arizona State Univ Tempe AZ USA

ISBN: (纸本)9781509049400

For deep-neural-network (DNN) processors [1-4], the product-sum (PS) operation predominates the computational workload for both convolution (CNVL) and fully-connect (FCNL) neural-network (NN) layers. this hinders the adoption of DNN processors to on the edge artificial-intelligence (AI) devices, which require low-power, low-cost and fast inference. Binary DNNs [5-6] are used to reduce computation and hardware costs for AI edge devices; however, a memory bottleneck still remains. In Fig. 31.5.1 conventional PE arrays exploit parallelized computation, but suffer from inefficient single-row SRAM access to weights and intermediate data. computing-in-memory (CIM) improves efficiency by enabling parallel computing, reducing memory accesses, and suppressing intermediate data. Nonetheless, three critical challenges remain (Fig. 31.5.2), particularly for FCNL. We overcome these problems by co-optimizing the circuits and the system. Recently, researches have been focusing on XNOR based binary-DNN structures [6]. Although they achieve a slightly higher accuracy, than other binary structures, they require a significant hardware cost (i.e. 8T-12T SRAM) to implement a CIM system. To further reduce the hardware cost, by using 6T SRAM to implement a CIM system, we employ binary DNN with 0/1-neuron and ±1-weight that was proposed in [7]. We implemented a 65nm 4Kb algorithm-dependent CIM-SRAM unit-macro and in-house binary DNN structure (focusing on FCNL with a simplified PE array), for cost-aware DNN AI edge processors. this resulted in the first binary-based CIM-SRAM macro with the fastest (2.3ns) PS operation, and the highest energy-efficiency (55.8TOPS/W) among reported CIM macros [3-4].

关键词： Random access memory Sensors Program processors Artificial intelligence Heuristic algorithms Hardware Video recording

来源：评论

学校读者我要写书评

暂无评论

PLZMA: A parallel Data Compression Method for Cloud computing 18th

PLZMA: A Parallel Data Compression Method for Cloud Computin...

引用

18th international conference on Algorithms and Architectures for parallel Processing (ICA3PP)

作者： Wang, Xin Gan, Lin Xu, Jingheng Yang, Jinzhe Xia, Maocai Fu, Haohuan Huang, Xiaomeng Yang, Guangwen Tsinghua Univ Dept Comp Sci & Technol Beijing Peoples R China Tsinghua Univ Key Lab Earth Syst Modeling Minist Educ Beijing Peoples R China Tsinghua Univ Dept Earth Syst Sci Beijing Peoples R China Natl Supercomp Ctr Wuxi Jiangsu Peoples R China Imperial Coll London Dept Comp London England Qingdao Natl Lab Marine Sci & Technol Lab Reg Oceanog & Numer Modeling Qingdao Peoples R China

ISBN: (纸本)9783030050573;9783030050566

Recent decades have seen the rapid development of cloud computing, resulting in a huge breakthrough for people to handle the data produced every second and everywhere. Meanwhile, data compression is becoming increasingly important, due to its great potential in benefiting both the network transportation and the storage. Based on the urgent demand in high-efficient compression method with balanced performance in both merits of compression time and ratio, this paper presents PLZMA, a parallel design of LZMA. Process-level and thread-level parallelisms are implemented according to the algorithm of LZMA, which have gained great improvement in compression time, while ensuring a fair compression ratio. Experimental results on real-world application showed that PLZMA is able to achieve more balanced performance over other famous methods. the parallel design is able to achieve a performance speedup of 8x over the serial baseline, using 12 threads.

关键词： Data compression parallel computing LZMA

来源：评论

学校读者我要写书评

暂无评论

Shortest Path Routing on OTIS Hyper Hexa-Cell 8

Shortest Path Routing on OTIS Hyper Hexa-Cell

引用

8th international conference on computing, Communication and networking Technologies (ICCCNT)

作者： Gupta, Ashish Sarkar, Bilcash Kanti Birla Inst Technol Dept Comp Sci & Engn Ranchi 835215 Bihar India

ISBN: (纸本)9781509030385

the Optical Transpose Interconnection Systems (OTIS) is a well known hybrid optoelectronic interconnection networks preserves the modular and scalable behavior of the network. the OTIS hyper hexa-cell [17] is recently proposed recursive optoelectronic network (related to the family of OTIS/Swapped interconnection networks), combines the most desirable and attractive properties of both OTIS and hyper hexa-cell networks. We present and analyze, in this paper, the shortest path routing algorithms over dh-dimensional OTIS HHC network, for all combination of the pair of processors.

关键词： OTIS Opto-electronic parallel Algorithm Hyper hexa-cell Time Complexity

来源：评论

学校读者我要写书评

暂无评论

computing-in-Memory with SRAM and RRAM for Binary Neural networks 14

Computing-in-Memory with SRAM and RRAM for Binary Neural Net...

引用

14th IEEE international conference on Solid-State and Integrated Circuit Technology, ICSICT 2018

作者： Sun, Xiaoyu Liu, Rui Peng, Xiaochen Yu, Shimeng Arizona State University TempeAZ85281 United States Georgia Institute of Technology AtlantaGA30332 United States

ISBN: (纸本)9781538644409

Recent advances in deep learning have shown that Binary Neural network (BNN) is able to provide a satisfying accuracy on various image datasets with a significant reduction in computation and memory cost. With both weights and activations binarized to +1 or -1 in BNNs, the high-precision multiply-and-accumulate (MAC) operations can be replaced by XNOR and bit-counting operations. In this work, we present two computing-in-memory (CIM) architectures with parallelized weighted-sum operation for accelerating the inference of BNN: 1) parallel XNOR-SRAM, where a customized 8T-SRAM cell is used as a synapse;2) parallel XNOR-RRAM, where a customized bit-cell consisting of 2T2R cells is used as a synapse. For large-scale weight matrices in neural networks, the array partition is necessary, where multi-level sense amplifiers (MLSAs) are employed as the intermediate interface for accumulating partial weighted sums. We explore various design options with different sub-array sizes and sensing bit-levels. Simulation results with 65nm CMOS PDK and RRAM models show that the system with 128×128 sub-array size and 3-bit MLSA can achieve 87.46% for an inspired VGG-like network on CIFAR-10 dataset, showing less than 1% degradation compared to the ideal software accuracy. the estimated energy-efficiency of XNOR-SRAM and XNOR-RRAM shows ~30× improvement compared to the corresponding conventional SRAM and RRAM architectures with sequential row-by-row read-out. © 2018 IEEE.

关键词： Static random access storage

来源：评论

学校读者我要写书评

暂无评论

Inferring Gene Regulatory networks Using Hybrid parallel computing 18th

Inferring Gene Regulatory Networks Using Hybrid Parallel Com...

引用

18th international conference on Computational Science and Its Applications (ICCSA)

作者： Ma, Jean C. W. K. Stefanes, Marco A. Higa, Carlos H. A. Rozante, Luiz C. S. Univ Fed Mato Grosso do Sul BR-79070900 Campo Grande MS Brazil Fed Univ ABC BR-09210580 Santo Andre SP Brazil

ISBN: (纸本)9783319951621;9783319951614

Gene regulatory networks (GRN) inference is an important bioinformatics problem, with many applications in system biology, in which the gene interactions need to be deduced from gene expression data, such as microarray data or RNA-Seq. Depending on the algorithm, the inference process may take a large amount of time due to the size of the networks and the complexity of the algorithm. the inference algorithm described in this work is based on the seed growing paradigm and has two steps: the seed growing and the inference step. We developed two parallel versions of the inference algorithm with the following approaches: Cluster of CPUs and a hybrid Multi CPU/GPUs. In tests performed in three databases of genes with different samples, these versions present good speedups, scalability, and robustness when compared with the sequential algorithm. Namely, for the seed growing step we achieved speedup of 12.7 with 16 nodes on Cluster of CPUs and speedup of 12.3 on hybrid Multi CPU/GPUs approach using 8 CPU/GPUs. For the inference step, we achieved speedups up to 10 on Cluster of CPUs.

关键词： Gene regulatory network Hybrid parallel computing GPU

来源：评论

学校读者我要写书评

暂无评论

ASIC Implementation of Efficient 16-parallel Fast FIR Algorithm Filter Structure 8

ASIC Implementation of Efficient 16-Parallel Fast FIR Algori...

引用

8th international conference on computing, Communication and networking Technologies (ICCCNT)

作者： Annangi, Swetha Puli, Ravisankar Guru Nanak Inst Technol Dept ECE Hyderabad Andhra Pradesh India First Pass Semicond Pvt Ltd Hyderabad Andhra Pradesh India

ISBN: (纸本)9781509030385

In this paper, a 144-tap 16-parallel Fast Finite Impulse Response (FIR) Algorithm (FFA) filter structure is designed using verilog HDL. the designed filter structure is simulated using XILINX ISE 14.7. the designed module is synthesized using CADENCE RTL Compiler and the application specific integrated circuit (ASIC) design of the proposed filter structure is implemented using CADENCE tool set on CADENCE GPDK45nm technology. By applying Fast FIR Algorithm, 65 percent of multipliers are reduced and the number of adders are increased. the adders occupy less silicon area than multipliers. Hence, the reduction in area is achieved by replacing the multipliers with adders. Further, the proposed 16 parallel FFA filter structure reduces the delay when compared to 16 parallel FIR filter structure without applying Fast FIR Algorithm. the proposed filter architecture occupies an area of 79220 sq. gm and consumes a power of 20mW at 333MHz when synthesized.

关键词： Keywords Finite Impulse Response (FIR) Fast FIR Algorithm (FFA) parallel FIR Application Specific Integrated Circuit (ASIC) Verilog HDL

来源：评论

学校读者我要写书评

暂无评论

Growing Neural Gas Based on Data Density 1

引用

17th international conference on Computer Information Systems and Industrial Management (CISIM)

作者： Vojacek, Lukas Drazdilova, Pavla Dvorsky, Jiri VSB Tech Univ Ostrava IT4Innovat 17 Listopadu 15-2172 Ostrava 70833 Czech Republic VSB Tech Univ Ostrava Dept Comp Sci 17 Listopadu 15-2172 Ostrava 70833 Czech Republic

ISBN: (数字)9783319999548

ISBN: (纸本)9783319999548;9783319999531

the size, complexity and dimensionality of data collections are ever increasing from the beginning of the computer era. Clustering methods, such as Growing Neural Gas (GNG) [10] that is based on unsupervised learning, is used to reveal structures and to reduce large amounts of raw data. the growth of computational complexity of such clustering method, caused by growing data dimensionality and the specific similarity measurement in a high-dimensional space, reduces the effectiveness of clustering method in many real applications. the growth of computational complexity can be partially solved using the parallel computation facilities, such as High Performance computing (HPC) cluster with MPI. An effective parallel implementation of GNG is discussed in this paper, while the main focus is on minimizing of interprocess communication which depends on the number of neurons and edges among neurons in the neural network. A new algorithm of adding neurons depending on data density is proposed in the paper.

关键词： Growing neural gas High-dimensional dataset High performance computing MPI Data density

来源：评论

学校读者我要写书评

暂无评论

PaSE: A parallel Speedup Estimation Framework for network-on-Chip based Multicore Systems 8

PaSE: A Parallel Speedup Estimation Framework for Network-on...

引用

8th international Green and Sustainable computing conference (IGSC)

作者： Dharb, Ghassan Mansoor, Naseef Shahriat, Sajeed Ganguly, Amlan Rochester Inst Technol Rochester NY 14623 USA

ISBN: (纸本)9781538634707

the massive integration of cores in multicore system has enabled chip designer to design systems while meeting the power-performance demands of the applications. However, full-system simulations traditionally used to evaluate the speedup of these systems are computationally expensive and time consuming. On the other hand, analytical speedup models such as Amdahl's law are powerful and fast ways to calculate the achievable speedup of these systems. However, Amdahl's Law disregards the communication among the cores that play a vital role in defining the achievable speedup with the multicore systems. To bridge this gap, in this work, we present PaSE a parallel speedup estimation framework for multicore systems that considers the latency of the network-on-Chip (NoC). To accurately capture the latency of the NoC we also propose a queuing theory based analytical model. We conduct a case study for a matrix multiplication application and evaluate and analyze the speedup from our framework.

关键词： Multicore network-on-Chip Speedup Latency

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共118页 << < 35 36 37 38 39 40 41 42 43 44 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：