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Toward automatic optimized code generation for multiprecision modular exponentiation on a GPU

Toward automatic optimized code generation for multiprecisio...

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2013 IEEE 37th Annual Computer Software and Applications conference, COMPSAC 2013

作者： Emmart, Niall Weems, Charles Computer Science Department University of Massachusetts Amherst MA 01003-4610 United States

ISBN: (纸本)9780769549798

Multiprocessing modular exponentiation has a variety of uses, including cryptography, prime testing and computational number theory. It is also a very costly operation to compute. GPU parallelism can be used to accelerate these computations, but to use the GPU efficiently, a problem must involve a significant number of simultaneous exponentiation operations. Handling a large number of TLS/SSL encrypted sessions in a data center is a significant problem that fits this profile. We have developed a framework that enables generation of highly efficient NVIDIA PTX implementations of exponentiation operations for different GPU architectures and problem instances. One of the challenges in generating such code is that PTX is not a true assembly language, but is instead a virtual instruction set that is compiled and optimized in different ways for different generations of GPU hardware. thus, the same PTX code runs with different levels of efficiency on different machines. And as the precision of the exponentiation values changes, each architecture has its own break-even points where a different algorithm or parallelization strategy must be employed. To make the code efficient for a given problem instance and architecture thus requires searching a multidimensional space of algorithms and configurations, by generating thousands of lines of carefully constructed PTX code for each combination, executing it, validating the numerical result, and evaluating its actual performance. Our framework automates much of this process, and produces exponentiation code that is up to six times faster than the best known hand-coded implementations. More importantly, the framework enables users to relatively quickly find the best configuration for each new GPU architecture. Our framework is also the basis for the eventual creation of a multiprocessing matrix arithmetic package for GPU cluster systems that will be portable across multiple generations of GPU. © 2013 IEEE.

关键词： Graphics processing unit

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Genome matching on modern architectures

Genome matching on modern architectures

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international conference on Systems, Signals and Image processing, IWSSIP

作者： Grigore Lupescu Bujor Pavaloiu Faculty of Engineering in Foreign Languages University POLITEHNICA of Bucharest Bucharest Romania BioMedical Engineering Centre University POLITEHNICA of Bucharest Bucharest Romania

Exact string matching algorithms are critical components in computational biology applications regarding the nucleotide or aminoacid sequences. the current paper presents a slightly modified version Boyer-Moore algorithm for string matching (in particular genomes) that has been optimized for a dual Xeon 5860. We highlight several ways to improve execution time and conclude based on our measurements that STTNI hardware instructions alongside core parallelism achieve most of the performance gain.

关键词： Multicore processing Program processors Bioinformatics Genomics Hardware parallel processing

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Ray-Tracing-Based Geospatial Optimization for Heterogeneous architectures Enhancing Situational Awareness

Ray-Tracing-Based Geospatial Optimization for Heterogeneous ...

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IEEE international conference on Computational Science and Engineering, CSE

作者： David A. Richie James A. Ross Song J. Park Dale R. Shires Brown Deer Technology Forest Hill MD Dynamics Research Corp. Andover MA APG U.S. Army Research Laboratory MD

this paper presents the implementation of ray tracing-based algorithms for multi-objective geospatial optimization targeting various many-core processing technologies such as graphics processing units, x86 multi-cores, and ARM processors. High performance is achieved through highly parallel core algorithms, executed on multiple compute devices across a heterogeneous architecture using low-level OpenCL kernels. algorithms for calculating line-of-sight ballistic threat, visual observability, ground plane extraction, and Markov chain Monte Carlo optimization provide an augmented geospatial intelligence and situational awareness in three-dimensional urban environments.

关键词： Optimization Ray tracing Surveillance Computer architecture Graphics processing units Kernel Observability

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parallel computation of electric potential in the EHD ion-drag micropump and the performance analysis of the parallel system

Parallel computation of electric potential in the EHD ion-dr...

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international conference on Information Technology in Asia (CITA)

作者： Shakeel Ahmed Kamboh Jane Labadin Andrew Ragai Henry Rigit Ling Teck Chaw Faculty of Engineering Universiti Malaysia Sarawak Kota Samarahan Sarawak Malaysia Faculty of Computer Science & Information Technology University of Malaya Kuala Lumpur Malaysia

ISBN: (纸本)9781479910908

the numerical solution of a computationally intensive model becomes more complex in terms of execution time required by a single processor. To speedup the computation, a suitable parallel computing architecture is required. this paper attempts to achieve a fast finite difference solution of electric potential in an EHD ion-drag micropump. A 2D Poisson's equation is solved on a cluster of low cost computers using MATLAB. Numerical solution is obtained for the different mesh refinements and then the execution time, communication time, speedup and efficiency of parallel system are analyzed. the results showed that the speedup and efficiency of the system increases by increasing the grid points. the results also reveal that for each data size there is an optimum number of workers for obtaining the parallel numerical solution in minimum processing time.

关键词： parallel processing Computational modeling Mathematical model Information technology Equations Computers MATLAB

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parallel B&B Algorithm for Hybrid Multi-core/GPU architectures

Parallel B&B Algorithm for Hybrid Multi-core/GPU Architectur...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： A. Bendjoudi M. Chekini M. Gharbi M. Mehdi K. Benatchba F. Sitayeb-Benbouzid N. Melab CERIST Research Center Algiers Algeria Ecole Suprieur d'Informatique (ESI) Oued Smar Algiers Algeria Université Lille1 France

B&B algorithms are well known techniques for exact solving of combinatorial optimization problems (COP). they perform an implicit enumeration of the search space instead of exhaustive one. Based on a pruning technique, they reduce considerably the computation time required to explore the whole search space. Nevertheless, these algorithms remain inefficient when dealing with large combinatorial optimization instances. they are time-intensive and they require a huge computing power to be solved optimally. Nowadays, multi-core-based processors and GPU accelerators are often coupled together to achieve impressive performances. However, classical B&B algorithms must be rethought to deal with their two divergent architectures. In this paper, we propose a new B&B approach exploiting both the multi-core aspect of actual processors and GPU accelerators. the proposed approaches have been executed to solve FSP instances that are well-known combinatorial optimization benchmarks. Real experiments have been carried out on an Intel Xeon 64-bit quad-core processor E5520 coupled to an Nvidia Tesla C2075 GPU device. the results show that our hybrid B&B approach speeds up the execution time up to ×123 over the sequential mono-core B&B algorithm.

关键词： Graphics processing units Upper bound Search problems parallel processing Multicore processing

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BC-BSP: A BSP-based parallel iterative processing system for big data on cloud architecture 1

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18th international conference on Database Systems for Advanced Applications, DASFAA 2013

作者： Bao, Yubin Wang, Zhigang Gu, Yu Yu, Ge Leng, Fangling Zhang, Hongxu Chen, Bairen Deng, Chao Guo, Leitao School of Information Science and Engineering Northeastern University Shenyang China Software Division Neusoft Corp. Shenyang China China Mobile Institute China Mobile Corp. Beijing China

ISBN: (数字)9783642402708

ISBN: (纸本)9783642402692

Many applications in real life can produce and collect large amount of data and many of them can be modeled by Graph. the number of vertexes of a graph could be several hundreds of millions to billions and the number of edges could be ten or more times of the number of its vertexes. A BSP-based system for large-scale data (especially graph data) parallel and iterative processing is discussed in this paper. the system has the ability to flexible configuration and the extendibility for functions and strategies (such as adjusting the parameters according to the volume of data and supporting multiple aggregation functions at the same time), to process large-scale data, to tolerate faults, to balance load, and to run clustering or classification algorithms on metric datasets. Lots of experiments are done to evaluate the extendibility of the system implemented in the paper, and the comparison between BC-BSP-based applications and MapReduce-based ones are made. the experimental results show that BSP-based applications have higher efficiency than that of MapReduce-based applications when the volume of data can be put in the memory during the course of processing;on the contrary the latter are better than the former, and the performance of BC-BSP platform outperforms Hama and Giraph. © Springer-Verlag 2013.

关键词： MapReduce

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Efficient homology computations on multicore and manycore systems

Efficient homology computations on multicore and manycore sy...

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international conference on High Performance Computing

作者： N. Anurag Murty Vijay Natarajan Sathish Vadhiyar Supercomputer Education and Research Centre

Homology computations form an important step in topological data analysis that helps to identify connected components, holes, and voids in multi-dimensional data. Our work focuses on algorithms for homology computations of large simplicial complexes on multicore machines and on GPUs. this paper presents two parallel algorithms to compute homology. A core component of both algorithms is the algebraic reduction of a cell with respect to one of its faces while preserving the homology of the original simplicial complex. the first algorithm is a parallel version of an existing sequential implementation using OpenMP. the algorithm processes and reduces cells within each partition of the complex in parallel while minimizing sequential reductions on the partition boundaries. Cache misses are reduced by ensuring data locality for data in the same partition. We observe a linear speedup on algebraic reductions and an overall speedup of up to 4.9× with 16 cores over sequential reductions. the second algorithm is based on a novel approach for homology computations on manycore/GPU architectures. this GPU algorithm is memory efficient and capable of extremely fast computation of homology for simplicial complexes with millions of simplices. We observe up to 40× speedup in runtime over sequential reductions and up to 4.5× speedup over REDHOM library, which includes the sequential algebraic reductions together with other advanced homology engines supported in the software.

关键词： Multicore processing Partitioning algorithms Microprocessors Graphics processing units Instruction sets Software algorithms

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Design space exploration of high level stream programs on parallel architectures: A focus on the buffer size minimization and optimization problem

Design space exploration of high level stream programs on pa...

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international Symposium on Image and Signal processing and Analysis

作者： Simone Casale Brunet Claudio Alberti Marco Mattavelli Jorn W. Janneck SCI-STI-MM École Polytechnique Fédérale de Lausanne Switzerland Department of Computer Science Lund Institute of Technology Sweden

this paper presents a dataflow design methodology and an associated co-exploration environment, focusing on the optimization of buffer sizes. the approach is applicable to dynamic dataflow designs and its performance is presented and validated by experimental results on the porting of an MPEG-4 Simple Profile decoder to the STM SthORM manycore platform. For the purpose of this work, the decoder has been written using the RVC-CAL dataflow language standardized by ISO/IEC. Starting from this high-level representation it is demonstrated how the buffer size configuration can be optimized, based on a novel buffer size minimization algorithm suitable for a very general class of dataflow programs.

关键词： Optimization Space exploration Algorithm design and analysis Minimization Computational modeling Streaming media Transform coding

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QbDJ: A Novel Framework for Handling Skew in parallel Join processing on Distributed Memory

QbDJ: A Novel Framework for Handling Skew in Parallel Join P...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Long Cheng Spyros Kotoulas Tomas E. Ward Georgios theodoropoulos National University of Ireland Maynooth Ireland IBM Res. Dublin Ireland Durham University UK

the performance of parallel distributed data management systems becomes increasingly important with the rise of Big Data. parallel joins have been widely studied both in the parallel processing and the database communities. Nevertheless, most of the algorithms so far developed do not consider the data skew, which naturally exists in various applications. State of the art methods designed to handle this problem are based on extensions to either of the two prevalent conventional approaches to parallel joins - the hash-based and duplication-based frameworks. In this paper, we introduce a novel parallel join framework, query-based distributed join (QbDJ), for handling data skew on distributed architectures. Further, we present an efficient implementation of the method based on the asynchronous partitioned global address space (APGAS) parallel programming model. We evaluate the performance of our approach on a cluster of 192 cores (16 nodes) and datasets of 1 billion tuples with different skews. the results show that the method is scalable, and also runs faster with less network communication compared to state-of-art PRPD approach in [1] under high data skew.

关键词： Arrays Distributed databases Histograms parallel processing Instruction sets Probes Silicon

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DSPACE hardware architecture for on-board real-time image/video processing in European space missions

DSPACE hardware architecture for on-board real-time image/vi...

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conference on Real-Time Image and Video processing

作者： Saponara, Sergio Donati, Massimiliano Fanucci, Luca Odendahl, Maximilian Leupers, Reiner Errico, Walter Univ Pisa Dept Informat Engn Via G Caruso 16 I-56122 Pisa Italy Consorzio Pisa Ric Scarl I-56122 Pisa Italy Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Sitael Aerosp Srl I-56122 Pisa Italy

ISBN: (纸本)9780819494290

the on-board data processing is a vital task for any satellite and spacecraft due to the importance of elaborate the sensing data before sending them to the Earth, in order to exploit effectively the bandwidth to the ground station. In the last years the amount of sensing data collected by scientific and commercial space missions has increased significantly, while the available downlink bandwidth is comparatively stable. the increasing demand of on-board real-time processing capabilities represents one of the critical issues in forthcoming European missions. Faster and faster signal and image processing algorithms are required to accomplish planetary observation, surveillance, Synthetic Aperture Radar imaging and telecommunications. the only available space-qualified Digital Signal Processor (DSP) free of international Traffic in Arms Regulations (ITAR) restrictions faces inadequate performance, thus the development of a next generation European DSP is well known to the space community. the DSPACE space-qualified DSP architecture fills the gap between the computational requirements and the available devices. It leverages a pipelined and massively parallel core based on the Very Long Instruction Word (VLIW) paradigm, with 64 registers and 8 operational units, along with cache memories, memory controllers and SpaceWire interfaces. Both the synthesizable VHDL and the software development tools are generated from the LISA high-level model. A Xilinx-XC7K325T FPGA is chosen to realize a compact PCI demonstrator board. Finally first synthesis results on CMOS standard cell technology (ASIC 180 nm) show an area of around 380 kgates and a peak performance of 1000 MIPS and 750 MFLOPS at 125MHz.

关键词： Digital Signal Processor space-qualified signal processing image processing GFLOP VLIW

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