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Accelerating the Performance of Stochastic Encoding-based Computations by Sharing Bits in Consecutive Bit Streams

Accelerating the Performance of Stochastic Encoding-based Co...

引用

IEEE international conference on Application-specific Systems, architectures and Processors

作者： Peng Li David J. Lilja Department of Electrical and Computer Engineering University of Minnesota Twin Cities Minneapolis MN USA 55812

ISBN: (纸本)9781479904945

Stochastic encoding represents a value using the probability of ones in a random bit stream. Computation based on this encoding has good fault-tolerance and low hardware cost. However, one of its major issues is long processing time. We have to use a long enough bit stream to represent a value to guarantee that random fluctuations introduce only small errors to final computation results. For example, for most digital image processing algorithms, we need a 512-bit stream to represent an 8-bit pixel value stochastically to guarantee that the final computation error is less than 5%. To solve this issue, this paper proposes to share bits between adjacent bit streams to represent adjacent deterministic values. For example, in image processing applications, the bit stream which represents the current pixel value can share parts of the bits in the bit stream which represents the previous pixel value. We use an image contrast stretching algorithm to evaluate this method. Our experimental results show that the proposed methods can improve the performance by 90%.

关键词： Computer reliability fault tolerance logic design stochastic computing digital image processing bit stream Image processing Logic design Fault tolerance Drill bits IMAGE CONTRAST arithmetic errors image processing algorithm streams random fluctuations processing time Binary digits

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MPSoC architecture for H.264/AVC intra prediction chain on SoCLiB platform and FPGA technology

MPSoC architecture for H.264/AVC intra prediction chain on S...

引用

international conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA)

作者： N. Belhadj M. Turki Z. Marrakchi M. Ali Ben Ayed N. Masmoudi H. Mehrez Laboratory of Electronics and Technology of Information from the National Engineering University of Sfax Tunisia Laboratory of Computer Sciences LIP6 University of Pierre and Marie Curie Paris France

Multiprocessor System on Chip (MPSoC) technology can present an interesting solution to reduce the computational time of complex applications. Execute the H.264/AVC encoder on MPSoC architecture, is becoming an interesting point of research that can mitigate its algorithmic complexity and to resolve the real time constraints. In this paper, we present an efficient MPSoC architecture for the intra prediction process which is an important module of the H.264/AVC video encoder, using Data Level parallelism (DLP) partitioning. this architecture is tested on an open platform for MPSoC architectures virtual designing (SoCLiB), and validated on FPGA technology. Experimental results show a gain of 74% in term of encoding speed when using four processors for coding a High Definition Video sequence (HDV) compared to uni-processor architecture.

关键词： Computer architecture Program processors Video coding Encoding Field programmable gate arrays parallel processing Partitioning algorithms

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Comparison between parallel and distributed molecular dynamics simulations of Lennard-Jones systems

Comparison between parallel and distributed molecular dynami...

引用

2012 IEEE 8th international conference on Intelligent Computer Communication and processing, ICCP 2012

作者： Baja, Vlad Gorgan, Dorian Beu, Titus Computer Science Department Technical University of Cluj-Napoca Cluj-Napoca Romania Faculty of Physics University Babes-Bolyai Cluj-Napoca Romania

ISBN: (纸本)9781467329514

this paper concerns mainly with parallel and distributed implementations of molecular dynamics simulations of the Lennard-Jones potential model. the reported research work studies and experiments different algorithms and parallelization techniques for shared memory and message passing architectures, and the programs are executed on single-core processors, multi-core processors, GPU, and GPU cluster. the solution based on efficient versions of the neighbor list algorithm and space division technique is further discussed. the obtained speedups for multi-core processor, GPU, and GPU cluster, relative to the single-core processor implementation of the program, are analyzed, and the advantages of the algorithms are highlighted. © 2012 IEEE.

关键词： Graphics processing unit

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Solving Sudoku in Reconfigurable Hardware

Solving Sudoku in Reconfigurable Hardware

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8th international conference on Computing and Networking Technology (ICCNT)

作者： Skliarova, Iouliia Vallejo, Tiago Sklyarov, Valery Univ Aveiro IEETA Dept Elect Telecommun & Informat P-3810193 Aveiro Portugal

ISBN: (纸本)9781467313261

In this paper we explore the effectiveness of solution of computationally intensive problems in FPGA (Field-Programmable Gate Array) on an example of Sudoku game. three different Sudoku solvers have been fully implemented and tested on a low-cost FPGA of Xilinx Spartan-3E family. the first solver is only able to deal with simple puzzles with reasoning, i.e. without search. the second solver applies breadth-first search algorithm and therefore has virtually no limitation on the type of puzzles which are solvable. We prove that despite the serial nature of implemented backtracking search algorithms, parallelism can be used efficiently. thus, the suggested third solver explores the possibility of parallel processing of search tree branches and boosts the performance of the second solver. the trade-offs of the designed solvers are analyzed, the results are compared to software and to other known implementations, and conclusions are drawn on how to improve the suggested architectures.

关键词： Sudoku FPGA breadth-first search parallel processing

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parallel Suffix Array Construction for Shared Memory architectures

Parallel Suffix Array Construction for Shared Memory Archite...

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19th international Symposium on String processing and Information Retrieval (SPIRE) / 8th Latin American Web Congress (LA-WEB)

作者： Osipov, Vitaly Karlsruhe Inst Technol Karlsruhe Germany

ISBN: (纸本)9783642341083;9783642341090

We present the design of the algorithm for constructing the suffix array of a string using manycore GPUs. Despite of the wide usage in text processing and extensive research over two decades there was a lack of efficient algorithms that were able to exploit shared memory parallelism (as multicore CPUs as manycore GPUs) in practice. To the best of our knowledge we developed the first approach exposing shared memory parallelism that significantly outperforms the state-of-the-art existing implementations for sufficiently large inputs. We reduced the suffix array construction problem to a number of parallel primitives such as prefix-sum, radix sorting, random gather and scatter from/to the memory. thus, the performance of the algorithm merely depends on the performance of these primitives on the particular shared memory architecture. We demonstrate its performance on manycore GPUs, but the method can also be applied for other parallel architectures, such as multicores, CELL or Intel MIC.

关键词： Text processing

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Image convolution processing: A GPU versus FPGA comparison

Image convolution processing: A GPU versus FPGA comparison

引用

8th Southern Programmable Logic conference, SPL 2012

作者： Russo, Lucas M. Pedrino, Emerson C. Kato, Edilson Roda, Valentin Obac Federal University of Sao Carlos - DC Rodovia Washington Luís km 235 - SP-310 13565-905 São Carlos - São Paulo Brazil Federal University of Rio Grande Do Norte - DEE Campus Universitário Lagoa Nova 59072-970 Natal - Rio Grande do Norte Brazil

ISBN: (纸本)9781467301862

Convolution is one of the most important operators used in image processing. With the constant need to increase the performance in high-end applications and the rise and popularity of parallel architectures, such as GPUs and the ones implemented in FPGAs, comes the necessity to compare these architectures in order to determine which of them performs better and in what scenario. In this article, convolution was implemented in each of the aforementioned architectures with the following languages: CUDA for GPUs and Verilog for FPGAs. In addition, the same algorithms were also implemented in MATLAB, using predefined operations and in C using a regular x86 quad-core processor. Comparative performance measures, considering the execution time and the clock ratio, were taken and commented in the paper. Overall, it was possible to achieve a CUDA speedup of roughly 200x in comparison to C, 70x in comparison to Matlab and 20x in comparison to FPGA. © 2012 IEEE.

关键词： Convolution

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Topic 10: parallel Numerical algorithms

引用

18th international conference on Euro-Par parallel processing

作者： Duff, Iain Gallopoulos, Efstratios di Serafino, Daniela Ucar, Bora Top Comm Air Force Base CO 80914 USA

ISBN: (纸本)9783642328206

the solution of large-scale problems in Computational Science and Engineering relies on the availability of accurate, robust and efficient numerical algorithms and software that are able to exploit the power offered by modern computer architectures. Such algorithms and software provide building blocks for prototyping and developing novel applications, and for improving existing ones, by relieving the developers from details concerning numerical methods as well as their implementation in new computing environments.

关键词： Computer architecture

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Design and Implementation of a parallel Priority Queue on Many-core architectures

Design and Implementation of a Parallel Priority Queue on Ma...

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19th international conference on High Performance Computing (HiPC)

作者： He, Xi Agarwal, Dinesh Prasad, Sushil K. Georgia State Univ Dept Comp Sci Atlanta GA 30303 USA

ISBN: (纸本)9781467323703;9781467323727

An efficient parallel priority queue is at the core of the effort in parallelizing important non-numeric irregular computations such as discrete event simulation scheduling and branch-and-bound algorithms. GPGPUs can provide powerful computing platform for such non-numeric computations if an efficient parallel priority queue implementation is available. In this paper, aiming at fine-grained applications, we develop an efficient parallel heap system employing CUDA. To our knowledge, this is the first parallel priority queue implementation on many-core architectures, thus represents a breakthrough. By allowing wide heap nodes to enable thousands of simultaneous deletions of highest priority items and insertions of new items, and taking full advantage of CUDA's data parallel SIMT architecture, we demonstrate up to 30-fold absolute speedup for relatively fine-grained compute loads compared to optimized sequential priority queue implementation on fast multicores. Compared to this, our optimized multicore parallelization of parallel heap yields only 2-3 fold speedup for such fine-grained loads. this parallelization of a tree-based data structure on GPGPUs provides a roadmap for future parallelizations of other such data structures.

关键词： data structures graphics processing units multiprocessing systems parallel architectures queueing theory

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parallel implementation of the TestU01 statistical test suite

Parallel implementation of the TestU01 statistical test suit...

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2012 IEEE 8th international conference on Intelligent Computer Communication and processing, ICCP 2012

作者： Suciu, Alin Toma, Radu Alexandru Marton, Kinga Department of Computer Science Technical University of Cluj-Napoca Cluj-Napoca Romania

ISBN: (纸本)9781467329514

As the need of high quality random number generators is constantly increasing especially for cryptographic algorithms, the development of high throughput randomness generators has to be combined with the development of high performance statistical test suites. Unfortunately the implementations of the most popular batteries of test suites are not focused on efficiency and high performance, do not benefit of the processing power offered by today's multi-core processors and tend to become bottlenecks in the processing of large volumes of data generated by various random number generators. Hence there is a stringent need for providing highly efficient statistical tests and our research efforts and results on improving and parallelizing the TestU01 test suite intend to fill this need. Experimental results show that the parallel version of TestU01 takes full advantage of the system's available processing power, reducing the execution time up to 4 times on the tested multicore systems. © 2012 IEEE.

关键词： Statistical tests

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GrABFAST: A CUDA based GPU Accelerated Fast Short Sequence Alignment Algorithm

GrABFAST: A CUDA based GPU Accelerated Fast Short Sequence A...

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19th international conference on High Performance Computing (HiPC)

作者： Narang, Ankur Soman, Jyothish Lahabar, Sheetal IBM India Res Labs Vasant Kunj Delhi 110070 India

ISBN: (纸本)9781467323703;9781467323727

Next Generation Sequencing (NGS) platforms typically produce short reads of size 50-150 base pairs (bp). the number of such short reads can be up to 6 billion per run. To align these short reads to a large genome is a computationally challenging problem. In this paper, we address this problem by considering the design and optimization of parallel sequence alignment on GPU based hybrid architectures. Even though the sequence alignment algorithm is inherently data-parallel, issues such as (a) space-time trade-offs in the Indexing schema, (b) need for fast candidate location search (CAL) on GPU, (c) maintaining low divergence along with low space for the dynamic programming based local alignment, make this a very challenging problem. We present the design of our novel parallel algorithm Graphics processor Accelerated BFAST (GrABFAST) for large scale read alignment that overcomes these challenges and demonstrates superior performance compared to Intel multicore architectures. Using 5 large genomes including those of Humans, Maize, Horse, Dog and Bacteria, we demonstrate a speedup of around 6x using Fermi Tesla C2070 GPUs vs the BFAST algorithm on 16 core Intel Xeon 5570 architecture.

关键词： dynamic programming graphics processing units multiprocessing systems parallel algorithms parallel architectures

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