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检索条件"任意字段=8th International Conference on Algorithms and Architectures for Parallel Processing"

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parallelism optimization with variables affinity graph for reconfigurable computing architecture

Parallelism optimization with variables affinity graph for r...

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international Joint conference on INC, IMS and IDC, NCM

作者： Shizhu Liu Shouyi Yin Chongyong Yin Leibo Liu Shaojun Wei National Laboratory for Information Science and Technology Institute of Microelectronics Tsinghua University Beijing China

In order to parallelism, generally, compiler considers the nodes which they want them to work in parallel. thus, the communication volume (CV) between variables is ignored. In this paper, we will make a variable affinity graph (VAG) which could imply CV. An approach which could cut VAG into optimization number pieces will be carried out. Using this approach, both CV and resource balance (RB) are considered and an optimization result could be computed. Our approach has been evaluated using a reconfigurable multi-core of four-tightly coupled processors, which can be simulated using a synthesized model or a cycle-accurate software simulator. Our results lead to an average 4-fold speed increase comparing to original systems, and an average 46% speed increase comparing DFG based optimal algorithm.

关键词： parallel processing Argon Wireless sensor networks

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parallel runtime verification of temporal properties for embedded software

Parallel runtime verification of temporal properties for emb...

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IEEE/ASME international conference on Mechtronic and Embedded Systems and Applications, MESA

作者： thomas Reinbacher Johannes Geist Patrick Moosbrugger Martin Horauer Andreas Steininger Department of Embedded Systems University of Applied Science Technikum Wien Wien Austria

We present a framework for parallel, non-intrusive runtime verification of past-time linear temporal logic (ptLTL) specifications that follows the trend of contemporary hardware designs which favors an increasing number of computing cores instead of a speedup of a single core. We introduce parallelism by sharing the truth values of common atomic propositions of the specification among multiple, low-hardware footprint micro-CPU cores that evaluate different specification items. the framework is generic and intended to work as an additional runtime verification engine that can be attached to the system under test by wire-tapping its memory interface. For better illustration of the approach we present a case-study where we verify some properties of a finite state machine that models a power windows system. the parallel framework yields a close to linear speedup for this use-case of up to 32 parallel verification units when compared to the conventional runtime verification, while the relative area overheads for a multi-core implementation remain very moderate.

关键词： Monitoring Runtime Hardware Observers Instruments Multicore processing Load management

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Real-time processing in dynamic ultrasound elastography: A GPU-based implementation using CUDA

Real-time processing in dynamic ultrasound elastography: A G...

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international Symposium on Signal processing and Its Applications (ISSPA)

作者： Emmanuel Montagnon Sami Hissoiny Philippe Després Guy Cloutier Laboratory of Biorheology and Medical Ultrasonics Université de Montréal Hospital Research Center (CRCHUM) Québec H2L 2W5 Canada Polytechnique Montreal Montreal QC CA Department of Radiation Oncology Université de Montréal Hospital (CHUM) Québec H2L 4M1 Canada

this paper addresses the computational cost of the normalized cross-correlation (NCC) algorithm in ultrasound elastography. parallel implementations of the NCC algorithm based on multicore architectures and a graphical processor unit (GPU) are formulated and applied to radio-frequency (RF) data from dynamic elastography experiments. Compared to single computer processor unit (CPU) performances, results show that parallel implementation of the NCC algorithm allows speedups of less than 5 for multi-threaded execution on CPU and up to 85 using a GPU. processing frame rates from 80 to 173 sec -1 have been achieved for large fields of view with good spatial resolution. the trade-off between accuracy, spatial resolution and computational cost in displacement estimation using the NCC algorithm therefore appears obsolete. Open source codes for implementing the NCC algorithm on GPU are made available at ***.

关键词： Graphics processing unit Ultrasonic imaging Instruction sets Heuristic algorithms Acoustics Computational efficiency Estimation

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Method of 3D mesh reconstruction from point cloud using elementary vector and geometry analysis

Method of 3D mesh reconstruction from point cloud using elem...

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international conference on Digital Content, Multimedia Technology and its Applications (IDC)

作者： N. Wongwaen S. Tiendee C. Sinthanayothin Image Technology Laboratory National Electronics and Computer Technology Center Pathum Thani Thailand Department of Computing Faculty of Liberal Arts and Sciences Kasetsart University Nakhon Pathom Thailand

the method of three dimensional mesh reconstruction is used to supplementing the 3D reconstruction or 3D scanning method, which only provide with point cloud in 3D model. However, the 3D models in mesh mode illustrate clearer appearance and can be used to obtain more information. In addition, the 3D reconstruction has been previously developed by employing the digital fringe pattern projection where the output was formed in the point cloud. therefore, this paper presents the computerized algorithms to construct the 3D mesh from the point cloud. the algorithm can be done by firstly dividing the point cloud into small volume for parallel calculation. Next, the points in each small volume are connected, which becomes the submesh and then integrated them together. the submesh in each small volume is produced by creating the initial triangle and then expanding triangular construction continually from each side (base) which has been previously generated. the expanded triangles must be satisfied some certain constrains. the point cloud which is filtered from the STL file format was tested using proposed method. the mesh reconstruction is shown with reasonable result.

关键词： Computational modeling Graphics processing unit

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On the parallel iterative finite difference algorithm for 2-D Poisson's equation with MPI cluster

On the parallel iterative finite difference algorithm for 2-...

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the international conference on Informatics and Systems (INFOS)

作者： N. H. Sweilam H. M. Moharram Sameh Ahmed Mathematics Department Faculty of Science Cairo University Giza Egypt

In this paper, a parallel iterative finite difference method (PIFD) for solving 2D Poisson's equation on a distributed system using Message Passing Interface (MPI) is investigated. this method is based on the domain decomposition method, where the 2D domain is divided into multiple sub-domains using horizontal and/or vertical axis depending on the available number of computer nodes. For interior points Poisson's equation is solved implicitly by four iterative schemes in combining with the boundary conditions. At the interface points of interior subdomains, Poisson's equation is solved by explicit iterative schemes. the proposed approach fulfills the suitability for the implementation on Linux PC cluster through the minimization of inter-process communication by restricting the exchange of data to the interface between the sub-domains. To examine the efficiency and accuracy of the iterative algorithm, several numerical experiments using different number of nodes of the Linux PC cluster are tested. the performance metrics clearly show the benefit of using the proposed approach on the Linux PC cluster in terms of execution time reduction and speedup with respect to the sequential running in a single PC.

关键词： Computers Program processors Poisson equations Iterative methods Finite difference methods Educational institutions parallel processing

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System modeling and multicore simulation using transactions

System modeling and multicore simulation using transactions

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international conference on Embedded Computer Systems: architectures, Modeling and Simulation (IC-SAMOS)

作者： Amine Anane El Mostapha Aboulhamid Yvon Savaria Université de Montréal Montréal Canada École Polytechnique de Montréal Montréal Canada

With the increasing complexity of digital systems that are becoming more and more parallel, a better abstraction to describe such systems has become a necessity. this paper shows how, by using the powerful mechanism of transactions as a concurrency model, and by taking advantage of .NET introspection and attribute programming capabilities, we were able to develop a system-level modeling and parallel simulation environment. We kept the same concepts to describe the architecture of high-level models, such as modules and communication channels. However, unlike SystemC, the behaviour is no longer described as processes and events but as transactions. We implemented scheduling algorithms in order to enable simulating a transactional models in parallel by taking advantage of a multicore machine. these algorithms take into account the dependency between transactions and the number of cores of the simulation machine. We studied two synchronisation strategies: one using locking and the other using partitioning. An experiment made on a WiFi 802.11a transmitter achieved a speedup of about 1.9 using two threads. With 8 threads, although the workload of individual transactions was not significant, we could reach a 5.1 speedup. When the workload is significant the speedup can reach 6.3.

关键词： Synchronization Semantics Multicore processing Scheduling algorithms Complexity theory System-on-a-chip Programming

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Optimisation and parallelism in synchronous digital circuit simulators

Optimisation and parallelism in synchronous digital circuit ...

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IEEE international conference on Computational Science and Engineering, CSE

作者： M. Chimeh Cordelia V. Hall John T. O'Donnell Sch. of Comput. Sci. Univ. of Glasgow Glasgow UK School of Computing Science University of Glasgow Glasgow UK University of Glasgow Glasgow Glasgow GB

Digital circuit simulation often requires a large amount of computation, resulting in long run times. We consider several techniques for optimising a brute force synchronous circuit simulator: an algorithm using an event queue that avoids recalculating quiescent parts of the circuit, a marking algorithm that is similar to the event queue but that avoids a central data structure, and a lazy algorithm that avoids calculating signals whose values are not needed. Two target architectures for the simulator are used: a sequential CPU, and a parallel GPGPU. the interactions between the different optimisations are discussed, and the performance is measured while the algorithms are simulating a simple but realistic scalable circuit.

关键词： Registers Arrays Integrated circuit modeling Clocks Graphics processing units Force Optimization

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An Improvement of OpenMP Pipeline parallelism with the BatchQueue Algorithm

An Improvement of OpenMP Pipeline Parallelism with the Batch...

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international conference on parallel and Distributed Systems (ICPADS)

作者： thomas Preud'Homme Julien Sopena Gaël thomas Bertil Folliot LIP6 Paris France

In the context of multicore programming, pipeline parallelism is a solution to easily transform a sequential program into a parallel one without requiring a whole rewriting of the code. the OpenMP stream-computing extension presented by Pop and Cohen proposes an extension of OpenMP to handle pipeline parallelism. However, their communication algorithm relies on Multiple-producer-Multiple-Consumer queues, while pipelined applications mostly deal with linear chains of communication, i.e., with only a single producer and a single consumer. To improve the performance of the OpenMP stream-extension, we propose to add a more specialized Single-Producer-Single-Consumer communication algorithm called Batch Queue and to select it for one-to-one communication. Our evaluation shows that Batch Queue is then able to improve the throughput up to a factor 2 on an 8-core machine both for example application and real applications. Our study shows therefore that using specialized and efficient communication algorithms can have a significant impact on the overall performance of pipelined applications.

关键词： parallel processing Pipelines throughput Benchmark testing Synchronization Multicore processing Scalability

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Mining bilingual linguistic patterns with aligned and parsed bilingual corpus

Mining bilingual linguistic patterns with aligned and parsed...

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international conference on Information Science and Digital Content Technology

作者： Bo Wang Fanqi Meng Yuexian Hou School of Computer Science and Technology Tianjin University 300072 China

ISBN: (纸本)9781467312882

Classical grammar for natural languages, which is defined by the linguistics, is widely used in many natural languages processing (NLP) tasks, such as information extraction, machine translation and parsing. the classical grammar is well defined but is context free and does not include the complex patterns which contain multiple linguistic units. On the other hand, there are also many simple patterns which are not included in the classical grammar but are useful in the NLP tasks. therefore, the recognition of special linguistic patterns from natural language is an important step in various NLP systems. We propose an unsupervised method to automatically discover the complex monolingual linguistic patterns from a classically parsed and aligned bilingual corpus. And all the patterns in one language are qualified by the other parallel language. A specialized and efficient algorithm is applied to mine the frequent bilingual subtrees in the forest and the found subtrees are formalized as the linguistic patterns.

关键词： Linguistics Natural Language processing natural languages context-free Alignment syntax Pragmatics efficient algorithm

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Development of a versatile low-power 24 GHz phased array front-end in 90 nm CMOS technology

Development of a versatile low-power 24 GHz phased array fro...

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Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS)

作者： G. Tasselli B. Wang S. Ghamari C. Robert C. Botteron P.A. Farine Electronics and Signal Processing Laboratory École Polytechnique Fédérale de Lausanne Neuchatel Switzerland

this paper deals with the development of a four-channel low-power Phased Array Front-End (PhA-FE) at 24 GHz, targeting both low-power radar sensors and battery powered transceiver applications. Typically, PhA-FEs are power hungry architectures due to multiple parallel RF channels in the FE and complex algorithms for beam steering or high bit-rate demodulation in the digital part. In contrast, we target in this paper applications where both beam steering algorithms and data demodulation are relatively simple and hence achievable with low-power digital signal processing. More specifically, we report on four significant building blocks of the architecture, a Low Noise Amplifier (LNA), a Vector Modulator Phase Shifter (VMPS), a Quadrature Voltage Controlled Oscillator (QVCO) and an Analogue to Digital Converter (ADC) that have been designed the first three in 90nm and the last in 180nm CMOS technology. the LNA shows 24.4 dB gain, 3.4 dB NF and -24.4 dBm input P1dB. the single quadrant VMPS has more than 90° of phase control range and shows less than 0.7 dB of gain variation over phase shifting. the QVCO which consumes less than 32mW, buffer included, has a tuning range of 8%. the 6bit 20 MS/s ADC consumes 1.8mW.

关键词： Gain Transceivers Computer architecture CMOS integrated circuits Radar Microprocessors Sensors

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