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A parallel irregular wavefront algorithm for importance sampling of probabilistic networks on GPU

A parallel irregular wavefront algorithm for importance samp...

引用

13th IEEE international Workshop on FTDCS 2011, the 8th international conference on ATC 2011, the 8th international conference on UIC 2011 and the 13th IEEE international conference on HPCC 2011

作者： Yu, Haohai Engelen, Robert Van Department of Computer Science Florida State University Tallahassee FL 32306 United States

ISBN: (纸本)9780769545387

Importance sampling is a widely-used method for probabilistic inference with Bayesian probabilistic networks. Importance sampling is relatively easy to parallelize and parallel GPU implementations yield significant speedups over single-CPU implementations. However, because of physical limitations of GPU memory size and bandwidth, the maximum speedups that can be achieved are bounded by the high data transfer requirements of these algorithms. In this paper, we propose and evaluate a new parallel irregular wave front algorithm for importance sampling of probabilistic networks on GPU. Performance results show that the proposed parallel algorithm achieves greater speedups due to the optimal local memory access compared to simple parallel GPU implementations. © 2011 IEEE.

关键词： Graphics processing unit

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parallel Implementation of External Sort and Join Operations on a Multi-core Network-Optimized System on a Chip

引用

11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Khorasani, Elahe Paulovicks, Brent D. Sheinin, Vadim Yeo, Hangu IBM TJ Watson Res Ctr Yorktown Hts NY 10598 USA

ISBN: (纸本)9783642246494

In a commercial Relational Database Management System (RDBMS), sort and join are the most demanding operations, and it is quite beneficial to improve the performance of external sort and external join algorithms that handle large input data sizes. this paper proposes parallel implementations of multithreaded external sort and external hash join algorithms to accelerate IBM DB2, one of leading RDBMSs, using an IBM Power Edge of Network (IBM PowerEN (TM)) Peripheral Component Interconnect Express (PCIe) card as an accelerator. the preliminary results show that the proposed parallel implementation of the algorithms on PowerEN (TM) PCIe card can speed up the DB2 sort and join performance about two times.

关键词： Sort Join Relational Database

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Comparison of three parallel Point-Multiplication algorithms on Conic Curves 1

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11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Li, Yongnan Xiao, Limin Qin, Guangjun Li, Xiuqiao Lei, Songsong Beihang Univ State Key Lab Software Dev Environm Beijing 100191 Peoples R China

ISBN: (数字)9783642246692

ISBN: (纸本)9783642246685

this paper makes a comparison of three parallel point-multiplication algorithms on conic curves over ring Zn. We propose one algorithm for paralleling point-multiplication by utilizing Chinese Remainder theorem to divide point-multiplication over ring Zn into two different point-multiplications over finite field and to compute them respectively. Time complexity and speedup ratio of this parallel algorithm are computed on the basis of our previous research about the basic parallel algorithms in conic curves cryptosystem. A quantitative performance analysis is made to compare this algorithm with two other algorithms we designed before. the performance comparison demonstrates that the algorithm presented in this paper can reduce time complexity of point-multiplication on conic curves over ring Zn and it is more efficient than the preceding ones.

关键词： conic curves ring Zn finite field Fp point-addition point-double point-multiplication Chinese Remainder theorem

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Emotional Contribution Process Implementations on parallel Processors 1

引用

11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Dominguez, Carlos Hassan, Houcine Albaladejo, Jose Marco, Maria Crespo, Alfons Univ Politecn Valencia Dept Informat Sistemas & Comp E-46071 Valencia Spain

ISBN: (数字)9783642246692

ISBN: (纸本)9783642246685

An emotional agent software architecture for real-time mobile robotic applications has been developed. In order to allow the agent to undertake more dynamically constrained application problem solving, the processor computation time should be reduced and the gained time is used for executing more complex processes. In this paper, the response time of the operating processes, in each attention cycle of the agent, is decreased by parallelizing the highly parallel processes of the architecture, namely, emotional contribution processes. the implementation of these processes has been evaluated in Field Programmable Gate Array (FPGA) and multicore processors.

关键词： FPGA Multicore Load balancing Robotics Agents Real-time

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Efficient parallel Implementations of Controlled Optimization of Traffic Phases

引用

11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Samra, Sameh El-Mahdy, Ahmed Gomaa, Walid Wada, Yasutaka Shoukry, Amin E JUST Alexandria Egypt Waseda Univ Fac Engn Sci Tokyo Japan

ISBN: (纸本)9783642246494

Finding optimal phase durations for a controlled intersection is a computationally intensive task requiring O(N-3) operations. In this paper we introduce cost-optimal parallelization of a dynamic programming algorithm that reduces the complexity to O(N-2). three implementations that span a wide range of parallel hardware are developed. the first is based on shared-memory architecture, using the OpenMP programming model. the second implementation is based on message passing, targeting massively parallel machines including high performance clusters, and supercomputers. the third implementation is based on the data parallel programming model mapped on Graphics processing Units (GPUs). Key optimizations include loop reversal, communication pruning, load-balancing, and efficient thread to processors assignment. Experiments have been conducted on 8-core server, IBM BlueGene/L supercomputer 2-node boards with 128 processors, and GPU GTX470 GeForce Nvidia with 448 cores. Results indicate practical scalability on all platforms, with maximum speed up reaching 76x for the GTX470.

关键词： parallel processing high performance computation traffic phases

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FPGA Technology And parallel Computing Towards Automatic Microarray Image processing

FPGA Technology And Parallel Computing Towards Automatic Mic...

引用

34th international conference on Telecommunications and Signal processing (TSP)

作者： Belean, Bogdan Borda, Monica LeGal, Bertrand Malutan, Raul Tech Univ Cluj Napoca Dept Commun 26-28 George Baritiu St Cluj Napoca 400027 Romania Univ Bordeaux Integrat Materiaux Syst Lab IMS Bordeaux France

ISBN: (纸本)9781457714115

Automation, computational time and cost are open subjects in microarray image processing. the present paper proposes image processing techniques together with their implementations in order to eliminate the shortcomings of the existing software platforms for microarray image processing: user intervention, increased computational time and cost. thus, for each step of microarray image processing, application-specific hardware architectures are designed aiming algorithms parallelization for fast processing. Computational time is estimated and compared with state of the art approaches. the proposed hardware architectures integrated inside microarray scanners deliver microarray image characteristics in an automated manner, excluding the need of an additional software platform. the FPGA technology was chosen for implementation, due to its parallel computation capabilities and ease of reconfiguration.

关键词： Microarray image processing parallel computing

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parallel points-to analysis for multi-core machines 11

Parallel points-to analysis for multi-core machines

引用

Proceedings of the 6th international conference on High Performance and Embedded architectures and Compilers

作者： Edvinsson, Marcus Lundberg, Jonas Löwe, Welf School of Computer Science Physics and Mathematics Linnaeus University 35195 Växjö Sweden

ISBN: (纸本)9781450302418

Static program analysis supporting software development is of ten part of edit-compile-cycles, and precise program analysis is time consuming. Points-to analysis is a data-flow-based static program analysis used to find object references in programs. Its applications include test case generation, compiler optimizations and program understanding, and more. Recent increases in processing power of desktop computers comes mainly from multiple cores. parallel algorithms are vital for simultaneous use of multiple cores. An efficient parallel points-to analysis requires sufficient work for each processing unit. the present paper presents a parallelized points-to analysis of object-oriented programs. It exploits that (1) different target methods of polymorphic calls and (2) independent control-flow branches can be analyzed in parallel. Carefully selected thresholds guarantee that each parallel thread has sufficient work to do and that only little work is redundant with other threads. Our experiments show that this approach achieves a maximum speed-up of 4.43 on 8 cores for a benchmark suite of Java programs. Copyright 2011 ACM.

关键词： parallel algorithms

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Distributed Load Balancing for parallel Agent-based Simulations

Distributed Load Balancing for Parallel Agent-based Simulati...

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19th international Euromicro conference on parallel, Distributed and Network-Based processing (PDP)

作者： Cosenza, Biagio Cordasco, Gennaro De Chiara, Rosario Scarano, Vittorio Univ Salerno ISISLab Dip Informat & Applicaz Renato M Capocelli I-84084 Fisciano SA Italy

ISBN: (纸本)9780769543284

We focus on agent-based simulations where a large number of agents move in the space, obeying to some simple rules. Since such kind of simulations are computational intensive, it is challenging, for such a contest, to let the number of agents to grow and to increase the quality of the simulation. A fascinating way to answer to this need is by exploiting parallel architectures. In this paper, we present a novel distributed load balancing schema for a parallel implementation of such simulations. the purpose of such schema is to achieve an high scalability. Our approach to load balancing is designed to be lightweight and totally distributed: the calculations for the balancing take place at each computational step, and influences the successive step. To the best of our knowledge, our approach is the first distributed load balancing schema in this context. We present both the design and the implementation that allowed us to perform a number of experiments, with up-to 1, 000, 000 agents. Tests show that, in spite of the fact that the load balancing algorithm is local, the workload distribution is balanced while the communication overhead is negligible.

关键词： Distributed Computing parallel algorithms Behavioral Simulations

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Efficient Decoding of QC-LDPC Codes Using GPUs

引用

11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Zhao, Yue Chen, Xu Sham, Chiu-Wing Tam, Wai M. Lau, Francis C. M. Hong Kong Polytech Univ Elect & Informat Engn Dept Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9783642246494

In this work, we propose an efficient quasi-cyclic LDPC (QC-LDPC) decoder simulator which runs on graphics processing units (GPUs). We optimize the data structures of the messages used in the decoding process such that both the read and write processes can be performed in a highly parallel manner by the GPUs. We also propose a highly efficient algorithm to convert the data structure of the messages from one form to another with very little latency. Finally, with the use of a large number of cores in the GPU to perform the simple computations simultaneously, our GPU-based LDPC decoder is found to run at around 100 times faster than a CPU-based simulator.

关键词： Belief propagation CUDA graphics processing unit (GPU) low-density parity-check codes LDPC decoder

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Binary Addition Chain on EREW PRAM 1

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11th international conference on algorithms and architectures for parallel processing (ICA3PP)

作者： Fathy, Khaled A. Bahig, Hazem M. Bahig, Hatem M. Ragb, A. A. Sinai Univ Fac Engn Dept Basic Sci Cairo Egypt Ain Shams Univ Fac Sci Dept Math Div Comp Sci Cairo Egypt Al Azhar Univ Fac Sci Dept Math Cairo Egypt

ISBN: (数字)9783642246692

ISBN: (纸本)9783642246685

An addition chain for a natural number x of n bits is a sequence of numbers a(0), a(1), ... , a(l), such that a(0) = 1, a(l) = x, and a(k) = a(i) + a(j) with 0 <= i, j < k <= l. the addition chain problem is what is the minimal number of additions needed to compute X starting from 1? In this paper, we present a new parallel algorithm to generate a short addition chain for x. the algorithm has running time O(log(2) n) using polynomial number processors under EREW PRAM (exclusive read exclusive write parallel random access machine). the algorithm is faster than previous algorithms and is based on binary method.

关键词： Addition chain binary method parallel algorithm EREW PRAM

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