检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

2,780 篇 会议
59 册 图书
46 篇 期刊文献

馆藏范围

2,883 篇 电子文献
2 种 纸本馆藏

日期分布

学科分类号

2,016 篇 工学
- 1,781 篇 计算机科学与技术...
- 945 篇 软件工程
- 297 篇 信息与通信工程
- 292 篇 电气工程
- 245 篇 电子科学与技术（可...
- 95 篇 控制科学与工程
- 52 篇 机械工程
- 49 篇 生物工程
- 44 篇 光学工程
- 41 篇 生物医学工程（可授...
- 37 篇 仪器科学与技术
- 28 篇 动力工程及工程热...
- 27 篇 化学工程与技术
- 21 篇 土木工程
- 20 篇 力学（可授工学、理...
- 19 篇 材料科学与工程（可...
- 18 篇 建筑学
542 篇 理学
- 386 篇 数学
- 107 篇 物理学
- 57 篇 生物学
- 48 篇 系统科学
- 32 篇 化学
- 32 篇 统计学（可授理学、...
197 篇 管理学
- 121 篇 管理科学与工程(可...
- 81 篇 图书情报与档案管...
- 56 篇 工商管理
51 篇 医学
- 42 篇 临床医学
- 16 篇 基础医学(可授医学...
19 篇 文学
17 篇 经济学
- 17 篇 应用经济学
15 篇 法学
- 14 篇 社会学
12 篇 农学
4 篇 教育学
3 篇 军事学

主题

345 篇 parallel process...
200 篇 parallel process...
192 篇 computer archite...
157 篇 graphics process...
153 篇 parallel archite...
113 篇 parallel algorit...
110 篇 graphics process...
107 篇 hardware
86 篇 image processing
81 篇 computational mo...
75 篇 signal processin...
71 篇 concurrent compu...
66 篇 instruction sets
65 篇 algorithm design...
65 篇 multicore proces...
63 篇 field programmab...
60 篇 parallel program...
58 篇 parallel computi...
53 篇 gpu
51 篇 optimization

机构

10 篇 natl univ def te...
8 篇 college of compu...
6 篇 hosei univ dept ...
6 篇 college of compu...
5 篇 univ aizu dept c...
5 篇 inria rennes
5 篇 national univers...
5 篇 natl univ def te...
5 篇 city university ...
5 篇 science and tech...
4 篇 chinese acad sci...
4 篇 school of comput...
4 篇 carleton univ sc...
4 篇 univ chinese aca...
4 篇 school of comput...
4 篇 charles univ pra...
4 篇 department of co...
4 篇 school of comput...
4 篇 hainan internati...
4 篇 purple mountain ...

作者

10 篇 liu jie
9 篇 jack dongarra
8 篇 roman wyrzykowsk...
7 篇 wang qinglin
7 篇 konrad karczewsk...
7 篇 quintana-orti en...
6 篇 gepner pawel
6 篇 peng shietung
6 篇 li kuan-ching
6 篇 li yamin
6 篇 chu wanming
6 篇 prasanna viktor ...
6 篇 rothermel kurt
6 篇 yang chao-tung
5 篇 dongarra jack
5 篇 olas tomasz
5 篇 hannig frank
5 篇 wanlei zhou
5 篇 qian depei
5 篇 ewa deelman

语言

2,822 篇 英文
51 篇 其他
17 篇 中文
1 篇 俄文

检索条件"任意字段=8th International Conference on Algorithms and Architectures for Parallel Processing"

共 2885 条记录，以下是1561-1570 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A graph-theory-based method for parallelizing the multiple-flow-direction algorithm on CUDA compatible graphics processing units

A graph-theory-based method for parallelizing the multiple-f...

引用

2011 IEEE international conference on Spatial Data Mining and Geographical Knowledge Services, ICSDM 2011 - In Conjunction with 8th Beijing international Workshop on Geographical Information Science, BJ-IWGIS 2011

作者： Zhan, Lijun Qin, Chengzhi State Key Laboratory of Resources and Environment Information System Chinese Academy of Sciences Beijing 100101 China Graduate School of the Chinese Academy of Sciences Beijing 100049 China

ISBN: (纸本)9781424483495

Flow direction algorithm based on gridded DEM is one kind of the most widely used algorithms in digital terrain analysis. Being a typical recursive algorithm, flow direction algorithm coded traditionally for sequential computation is very time consuming, especially for application on the gridded DEM of large-area with high spatial resolution. Recently, the graphics processing units (GPUs) were applied to speeding up the execution of single flow direction algorithm (SFD) by parallel computing based on compute unified device architecture (CUDA). Although multiple flow direction (MFD) algorithms perform generally better than SFD, parallel MFD algorithm on GPU hasn't been reported. In this paper, first we designed a CUDA-based parallel implementation on the NVIDIA GPU of a widely-used MFD algorithm (FD8) by using the parallelization strategy of the existing CUDA-based parallel SFD algorithm. Further analysis shows that this parallelization strategy has a problem of computing redundancy. then, we proposed a graph-theory-based parallel implementation of FD8 algorithm in which the problem of computing redundancy could be released. the application result shows that the proposed graph-theory-based parallel FD8 algorithm gets faster acceleration than the parallel FD8 algorithm using the parallelization strategy of the existing CUDA-based parallel SFD algorithm, and performs much faster than the traditional serial FD8 algorithm. © 2011 IEEE.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Semi-supervised learning for word sense disambiguation using parallel corpora

Semi-supervised learning for word sense disambiguation using...

引用

2011 8th international conference on Fuzzy Systems and Knowledge Discovery, FSKD 2011, Jointly with the 2011 7th international conference on Natural Computation, ICNC'11

作者： Yu, Mo Wang, Shu Zhu, Conghui Zhao, Tiejun MOE-MS Key Laboratory of Natural Language Processing and Speech Harbin Institute of Technology Harbin China

ISBN: (纸本)9781612841816

the Application of word sense disambiguation (WSD) methods based on supervised machine learning are limited by the difficulties in defining sense tags and acquiring labeled data for training. In this paper, the two problems of WSD are solved in a semi-supervised learning framework with the help of parallel corpora. the sense tags are defined automatically according to the results of word alignment on the parallel corpora. And label propagation, a graph-based semi-supervised algorithm, is employed. the experiments show that our method achieves great improvement on Chinese WSD tasks and the performances get significant growth when the scale of monolingual sentences is increasing. © 2011 IEEE.

关键词： Supervised learning

来源：评论

学校读者我要写书评

暂无评论

A GPU accelerated PSO with application to economic dispatch problem

A GPU accelerated PSO with application to economic dispatch ...

引用

2011 16th international conference on Intelligent System Applications to Power Systems, ISAP 2011

作者： Papadakis, S.E. Bakrtzis, A.G. Industrial Informatics Department Technological Institute of Kavala Greece Department of Electrical Engineering Aristotle University of Thessaloniki Greece

this paper investigates the use of Graphics processing Units (GPUs) as general purpose parallel architectures, for the acceleration of the solution of the Economic Dispatch problem (ED) via stochastic search algorithms. the Comprehensive Learning Particle Swarm Optimizer (CLPSO) is used as host process to carry out the optimization task. At every time of the evolution a parallel graphics card speeds up the optimization process by calculating, in parallel, the fitness value of all particles. Two different approaches are investigated: a fine-grained parallelism and a coarse-grained one. the results demonstrate that GPUs can be applied with success to speed up computationally intensive problems in electric energy systems. © 2011 IEEE.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

New Multithreaded Ordering and Coloring algorithms for Multicore architectures

引用

17th international Euro-Par conference on parallel processing

作者： Patwary, Md. Mostofa Ali Gebremedhin, Assefaw H. Pothen, Alex Univ Bergen N-5020 Bergen Norway Purdue Univ W Lafayette IN USA

ISBN: (纸本)9783642233975

We present new multithreaded vertex ordering and distance-k graph coloring algorithms that are well-suited for multicore platforms. the vertex ordering techniques rely on various notions of "degree", are known to be effective in reducing the number of colors used by a greedy coloring algorithm, and are generic enough to be applicable to contexts other than coloring. We employ approximate degree computation in the ordering algorithms and speculation and iteration in the coloring algorithms as our primary tools for breaking sequentiality and achieving effective parallelization. the algorithms have been implemented using OpenMP, and experiments conducted on Intel Nehalem and other multicore machines using various types of graphs attest that the algorithms provide scalable runtime performance. the number of colors the algorithms use is often close to optimal. the techniques used for computing the ordering and coloring in parallel are applicable to other problems where there is an inherent ordering to the computations that needs to be relaxed for increasing concurrency.

关键词： Software architecture

来源：评论

学校读者我要写书评

暂无评论

parallel Training of Artificial Neural Networks Using Multithreaded and Multicore CPUs

Parallel Training of Artificial Neural Networks Using Multit...

引用

10th international conference on Adaptive and Natural Computing algorithms

作者： Schuessler, Olena Loyola, Diego German Aerosp Ctr Inst Remote Sensing D-82234 Wessling Germany

ISBN: (纸本)9783642202810

this paper reports on methods for the parallelization of artificial neural networks algorithms using multithreaded and multicore CPUs in order to speed up the training process. the developed algorithms were implemented in two common parallel programming paradigms and their performances are assessed using four datasets with diverse amounts of patterns and with different neural network architectures. All results show a significant increase in computation speed. which is reduced nearly linear with the number of cores for problems with very large training datasets.

关键词： Neural network training multithreading and multicore Pthreads and OpenMP parallelization

来源：评论

学校读者我要写书评

暂无评论

EPUMA embedded parallel DSP processor with Unique Memory Access

EPUMA embedded parallel DSP processor with Unique Memory Acc...

引用

8th international conference on Information, Communications and Signal processing, ICICS 2011

作者： Liu, Dake Karlsson, Andreas Sohl, Joar Wang, Jian Petersson, Magnus Zhou, Wenbiao Dept of Electrical Engineering Linkping University Sweden ASIP College of Information and Electronics Beijing Institute of Technologies China

ISBN: (纸本)9781457700309

Computing unto 100GOPS without cooling is essential for high-end embedded systems and much required by markets. A novel master-slave multi-SIMD architecture and its kernel (template) based parallel programming flow is thus introduced as a parallel signal processing platform, ePUMA, embedded parallel DSP processor with Unique Memory Access. It is an on chip multi-DSP-processor (CMP) targeting to predictable signal processing for communications and multimedia. the essential technologies are to separate the processing of control stream from parallel computing, and to separate parallel data access from parallel arithmetic computing kernels. By separations, the computation and data access can be orthogonal both in hardware and in programs. Orthogonal operations can therefore be executed in parallel and the run time cost of data access can be minimized. Benchmark shows that the computing performance therefore reaches about 80% of the hardware limit. Less than 40% of the hardware limit can be reached by normal processors. the unique SIMD memory subsystem architecture offers programmable conflict free parallel data accesses. Programming flow and tools are also developed to support coding on the unique hardware architecture. A prototype on FPGA shows especially high performance over silicon cost. © 2011 IEEE.

关键词： Embedded systems

来源：评论

学校读者我要写书评

暂无评论

parallelizing TUNAMI-N1 using GPGPU

Parallelizing TUNAMI-N1 using GPGPU

引用

13th IEEE international Workshop on FTDCS 2011, the 8th international conference on ATC 2011, the 8th international conference on UIC 2011 and the 13th IEEE international conference on HPCC 2011

作者： Gidra, Harsh Haque, Israrul Kumar, Nitin P. Sargurunathan, M. Gaur, M.S. Laxmi, Vijay Zwolinski, M. Singh, Virendra Department of Computer Engineering Malaviya National Institute of Technology Jaipur India

ISBN: (纸本)9780769545387

We present a high performance tsunami-prediction system using General Purpose Graphics processing Units (GPGPU). It is based on TUNAMI-N1, a Numerical Analysis Model for Investigation of near-field tsunamis. It uses linear shallow water wave equations, commonly accepted approximation for tsunami propagation, taking the input from a bathymetry file containing a large data set. Due to the largeness of the data set, the model is more amenable to parallelization. the system maps the TUNAMI-N1 model into the massively parallel GPU architecture using Nvidia CUDA framework. It employs multiple kernels that contain inherently parallel portion of the model and uses the concepts of data and hybrid parallelism to fully exploit the hardware capabilities of the GPUs. Experimental results show that our system achieves a speed up of six times. © 2011 IEEE.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Ultra Low Power QC-LDPC Decoder with High parallelism

Ultra Low Power QC-LDPC Decoder with High Parallelism

引用

24th IEEE international System-on-Chip conference (SOCC)

作者： Cui, Ying Peng, Xiao Chen, Zhixiang Zhao, Xiongxin Lu, Yichao Zhou, Dajiang Goto, Satoshi Waseda Univ Grad Sch Informat Prod & Syst Kitakyushu Fukuoka Japan

ISBN: (纸本)9781457716171

this paper presents a novel high parallel decoder architecture for the quasi-cyclic low-density parity-check (QC-LDPC) codes defined in WiMAX system. Based on the turbo-decoding message passing (TDMP) algorithm, this architecture costs 8 similar to 16 clock cycles for each iteration in the decoding process. In the normalized comparison with the state-of-art work, this design achieves up to 6.5x higher parallelism and 76% power reduction. the energy/bit/iteration of this design is only 1/5 of the previous work.

关键词： Clocks Decoding Hardware Logic gates parallel architectures parallel processing Parity check codes QC LDPC decoder TDMP algorithm WiMAX WiMax cyclic codes low density parity check codes message passing parallel decoder architecture parity check codes quas

来源：评论

学校读者我要写书评

暂无评论

Using COTS graphics processing units in signal analysis workstations

Using COTS graphics processing units in signal analysis work...

引用

47th Annual international Telemetering conference and Technical Exhibition - Telemetry: Blending the Art with Science and Technology, ITC 2011

作者： Crook, Alex Kissinger, Gregory Kosbar, Kurt Telemetry Learning Center Department of Electrical and Computer Engineering Missouri University of Science and Technology Rolla MO United States

Commercial off-the-shelf (COTS) graphics processing units (GPU) perform the signal processing operations needed for video games and similar consumer applications. the high volume and competitive nature of that industry have produced inexpensive GPUs with impressive amounts of signal processing power. these devices use parallel processing architectures to execute DSP algorithms far faster than single, or even multi-core central processing units typically found in workstations. this paper describes a project which improves the performance of a radar telemetry application using the NVidiaTM brand GPU and CUDATM software, although the results could be extended to other devices.

关键词： Program processors

来源：评论

学校读者我要写书评

暂无评论

Performance Analysis and Optimization of Molecular Dynamics Simulation on Godson-T Many-core Processor 11

Performance Analysis and Optimization of Molecular Dynamics ...

引用

8th ACM international conference on Computing Frontiers (CF)

作者： Peng, Liu Nakano, Aiichiro Tan, Guangming Vashishta, Priya Fan, Dongrui Zhang, Hao Kalia, Rajiv K. Song, Fenglong Chinese Acad Sci Inst Comp Technol Key Lab Comp Syst & Architecture Beijing 100190 Peoples R China Univ Southern Calif Collaboratory Adv Comp & Simulat Los Angeles CA 90089 USA

ISBN: (纸本)9781450306980

Molecular dynamics (MD) simulation has broad applications, but its irregular memory-access pattern makes performance optimization a challenge. this paper presents a joint application/architecture study to enhance on-chip parallelism of MD on Godson-T-like many-core architecture. First, a preprocessing leveraging an adaptive divide-and-conquer framework is designed to exploit locality through memory hierarchy with software controlled memory. then we propose three incremental optimization strategies: (1) a novel data-layout to re-organize linked-list cell data structures to improve data locality;(2) an on-chip locality-aware parallel algorithm to enhance data reuse;and (3) a pipelining algorithm to hide latency to shared memory. Experiments on Godson-T simulator exhibit strong-scaling parallel efficiency 0.99 on 64 cores, which is confirmed by an FPGA emulator. Detailed analysis shows that optimizations utilizing architectural features to maximize data locality and to enhance data reuse benefit scalability most. Furthermore, a simple performance model suggests that the optimization scheme is likely to scale well toward exascale. Certain architectural features are found essential for these optimizations, which could guide future hardware developments.

关键词： C.1.2 [Processor architectures]: Multiple Data Stream architectures D.1.3 [Programming Techniques]: Concurrent Programming Performance

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共289页 << < 153 154 155 156 157 158 159 160 161 162 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：