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检索条件"任意字段=8th International Conference on Algorithms and Architectures for Parallel Processing"

共 2885 条记录，以下是1691-1700 订阅

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Self-Organizing Networks: State-of-the-Art, Challenges and Perspectives

Self-Organizing Networks: State-of-the-Art, Challenges and P...

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8th international conference on Communications

作者： Marchetti, Nicola Prasad, Neeli Rashmi Johansson, Johan Cai, Tao Aalborg Univ Ctr TeleInFrastruktur Aalborg Denmark Huawei Technol AB Kista Sweden

ISBN: (纸本)9781424463633

In this paper, a general overview of Self-Organizing Networks (SON), and the rationale and state-of-the-art of wireless SON are first presented. the technical and business requirements are then briefly treated, and the research challenges within the field of SON are highlighted. thereafter, the relation between SON and Cognitive Networks (CN) is covered. At last, the application of Algorithmic Information theory (AIT) as a possible theoretical tool to support SON in addressing the growing complexity of networks is discussed.

关键词： parallel processing systems

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16th international Euro-Par conference on parallel processing, Euro-Par 2010

16th International Euro-Par Conference on Parallel Processin...

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16th international Euro-Par conference on parallel processing, Euro-Par 2010

ISBN: (纸本)9783642152764

the proceedings contain 104 papers. the special focus in this conference is on parallel processing. the topics include: A parallel implementation of the Jacobi-Davidson eigensolver and its application in a plasma turbulence code;scheduling parallel eigenvalue computations in a quantum chemistry code;Scalable parallelization strategies to accelerate NuFFT data translation on multicores;multicore and Manycore Programming;javaSymphony: A programming and execution environment for parallel and distributed many-core architectures;scalable producer-consumer pools based on elimination-diffraction trees;productivity and performance: Improving consumability of hardware transactional memory through a real-world case study;exploiting fine-grained parallelism on cell processors;optimized on-chip-pipelined mergesort on the cell/B.E.;transactional mutex locks;Near-optimal placement of MPI processes on hierarchical NUMA architectures;parallel enumeration of shortest lattice vectors;A parallel GPU algorithm for mutual information based 3D nonrigid image registration;Multi-GPU and multi-CPU parallelization for interactive physics simulations;Long DNA sequence comparison on multicore architectures;adaptive fault tolerance for many-core based space-borne computing;Maestro: Data orchestration and tuning for openCL devices;multithreaded Geant4: Semi-automatic transformation into scalable thread-parallel software;parallel exact time series motif discovery;optimized dense matrix multiplication on a many-core architecture;exceptions for algorithmic skeletons;a language-based tuning mechanism for task and pipeline parallelism;A study of a software cache implementation of the OpenMP memory model for multicore and manycore architectures;Programming CUDA-based GPuS to simulate two-layer shallow water flows;theory and algorithms for parallel computation;analysis of multi-organization scheduling algorithms;Area-maximizing schedules for series-parallel DAGs;parallel Selection by Regular Sampling;a

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16th international Euro-Par conference on parallel processing, Euro-Par 2010

16th International Euro-Par Conference on Parallel Processin...

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16th international Euro-Par conference on parallel processing, Euro-Par 2010

ISBN: (纸本)9783642152900

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Using the CPU and GPU for Real-Time Video Enhancement on a Mobile Computer

Using the CPU and GPU for Real-Time Video Enhancement on a M...

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IEEE 10th international conference on Signal processing

作者： Bachoo, Asheer CSIR Optron Sensor Syst Def Peace Safety & Secur Pretoria South Africa

ISBN: (纸本)9781424458981

Real-time video enhancement is generally achieved using costly specialized hardware that have specific functions and outputs. Commercial off-the-shelf hardware, such as desktop computers with Graphics processing Units (GPUs), are also commonly used as cost effective solutions for real-time video processing. In the past, the limitations in computer hardware meant that real-time video enhancement was mainly done on desktop GPUs with minimal use of the Central processing Unit (CPU). these algorithms were simple and easily parallelizable in nature, which enabled them to achieve real-time performance. However, complex enhancement algorithms also require the sequential processing of data and this cannot be easily achieved in real-time on a GPU. In this paper, the current advances in mobile CPU and CPU hardware are used to implement video enhancement algorithms in a new way on a mobile computer. Both the CPU and GPU are used effectively to achieve real. time performance for complex image enhancement algorithms that require both sequential and parallel processing operations. Results are presented for histogram equalization, local adaptive histogram equalization, contrast enhancement using tone mapping and exposure fusion of multiple 8-bit grey scale videos of size up to 1600x1200 pixels.

关键词： central processing unit computer graphic equipment contrast enhancement desktop computers exposure fusion graphics processing units image enhancement image enhancement local adaptive histogram equalization mobile computer mobile computing parallel processing parallel processing sequential processing tone mapping video enhancement video signal processing

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Accelerating Dock6's Amber Scoring with Graphic processing Unit

Accelerating Dock6's Amber Scoring with Graphic Processing U...

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10th international conference on algorithms and architectures for parallel processing

作者： Yang, Hailong Li, Bo Wang, Yongjian Luan, Zhongzhi Qian, Depei Chu, Tianshu Beihang Univ Sino German Joint Software Inst Dept Comp Sci & Engn Beijing 100191 Peoples R China

ISBN: (纸本)9783642131189

In the drug discovery field, solving the problem of virtual screening is a long term-goal. the scoring functionality which evaluates the fitness of the docking result is one of the major challenges in virtual screening. In general, scoring functionality in docking requires large amount of floating-point calculations and usually takes several weeks or even months to be finished. this time-consuming disadvantage is unacceptable especially when highly fatal and infectious virus arises such as SARS and H1N1. this paper presents how to leverage the computational power of GPU to accelerate Dock6 [1]'s Amber [2] scoring with NVIDIA CUDA [3] platform. We also discuss many factors that will greatly influence the performance after porting the Amber scoring to GPU, including thread management, data transfer and divergence hidden. Our GPU implementation shows a 6.5x speedup with respect to the original version running on AMD dual-core CPU for the same problem size.

关键词： Graphics processing unit

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parallelization Strategies for Computing PageRank

Parallelization Strategies for Computing PageRank

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7th international conference on Engineering Computational Technology

作者： Migallon, H. Migallon, V. Palomino, J. A. Penades, J. Univ Miguel Hernandez Dept Phys & Comp Architectures Alicante Spain Univ Alicante Dept Comp Sci & Artificial Intelligence Alicante Spain

ISBN: (纸本)9781905088416

the PageRank algorithm for determining the importance of Web pages has become a central technique in Web search. this algorithm uses the Power method to compute successive iterates that converge to the principal eigenvector of the Markov chain representing the Web link graph. In this paper different parallel implementations of the PageRank algorithm are proposed. Synchronous and asynchronous implementations of the Power method are analyzed using different data distribution strategies. the algorithms described here have been implemented on two parallel computers. the first platform is a DELL PowerEdge 2900 with two Quad-Core Intel Xeon 5320 sequence processors at up to 1.86 GHz. the second platform is a Beowulf cluster of 6 nodes Intel x86 connected through a 1 Gb/sec. Each node consists of two Intel Xeon Quad-Core processors at up to 2.60 GHz with 8 GB of RAM. the reported experiments show the behaviour of the designed algorithms for realistic test data on both shared and distributed architectures.

关键词： PageRank parallel algorithms Power method shared memory distributed memory sychronous and asynchronous iterations

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A comparison of pipelined parallel and iterative CORDIC design on FPGA

A comparison of pipelined parallel and iterative CORDIC desi...

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2010 5th international conference on Industrial and Information Systems, ICIIS 2010

作者： Bhakthavatchalu, Ramesh Sinith, M.S. Nair, Parvathi Jismi, K. Dept. of ECE Amrita Vishwa Vidyapeetham Amritapuri Kollam-690525 Kerala India

ISBN: (纸本)9781424466535

Many hardware efficient algorithms exists for hardware signal processing architecture. Among these algorithm is a set of shift-add algorithms collectively known as CORDIC (COrdinate Rotation for Digital Computers) for computing a wide range of functions including certain trigonometric, hyperbolic, linear and logarithmic functions. the paper compares the different CORDIC architectures with respect to their area, speed, and data throughput performance especially in three different major styles iterative, parallel and pipelined structures. All three designs were designed in VHDL, simulated using Modelsim simulator and Implemented using Xilinx FPGA synthesis and Synopsis ASIC synthesis tools. ©2010 IEEE.

关键词： Digital computers

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Balanced Multi-process parallel Algorithm for Chemical Compound Inference with Given Path Frequencies

Balanced Multi-process Parallel Algorithm for Chemical Compo...

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10th international conference on algorithms and architectures for parallel processing

作者： Zhou, Jiayi Yu, Kun-Ming Lin, Chun Yuan Shih, Kuei-Chung Tang, Chuan Yi Chung Hua Univ Dept Comp Sci & Informat Engn Hsinchu 300 Taiwan Natl Tsing Hua Univ Dept Comp Sci Hsinchu 30013 Taiwan Chang Gung Univ Dept Comp Sci & Informat Engn Taoyuan Taiwan

ISBN: (纸本)9783642131356

To enumerate chemical compounds with given path frequencies is a fundamental procedure in Chemo- and Bio-inforrnatics. the applications include structure determination, novel molecular development, etc. the problem complexity has been proven as NP-hard. Many methods have been proposed to solve this problem. However, most of them are heuristic algorithms. Fujiwara et al. propose a sequential branch-and-bound algorithm. Although it reaches all solutions and avoids exhaustive searching, the computation time still increases significantly when the number of atoms increases. Hence, in this paper, a parallel algorithm is presented for solving this problem. the experimental results showed that computation time was reduced even when more processes were launched. Moreover, the speed-up ratio for most of the test cases was satisfactory and, furthermore, it showed potential for use in drug design.

关键词： Branch-and-bound algorithm load-balancing chemical compound inference drug design

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Impact of Multimedia Extensions for Different processing Element Granularities on an Embedded Imaging System

Impact of Multimedia Extensions for Different Processing Ele...

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10th international conference on algorithms and architectures for parallel processing

作者： Kim, Jong-Myon Univ Ulsan Sch Comp Engn & Informat Technol Ulsan 680749 South Korea

ISBN: (纸本)9783642131189

Multimedia applications are among the most dominant computing workloads driving innovations in high performance and cost effective systems. In this regard, modern general-purpose microprocessors have included multimedia extensions (e.g., MMX, SSE, VIS, MAX, ALTIVEC) to their instruction set architectures to improve the performance of multimedia with little added cost to microprocessors. Whereas prior studies of multimedia extensions have primarily focused on a single processor, this paper quantitatively evaluates the impact of multimedia extensions on system performance and efficiency for different number of processing elements (PEs) within an integrated multiprocessor array. this paper also identifies the optimal PE granularity for the array system and implementation technology in terms of throughput, area efficiency, and energy efficiency using architectural and workload simulation. Experimental results with cycle accurate simulation and technology modeling show that MMX-type instructions (a representative Intel's multimedia extensions) achieve an average speedup ranging from 1.24x (at a 65,536 PE system) to 5.65x (at a 4 PE system) over the baseline performance. In addition, the MMX-enhanced processor array increases both area and energy efficiency over the baseline for all the configurations and programs. Moreover, the highest area and energy efficiency are achieved at the number of PEs between 256 and 1,024. these evaluation techniques composed of performance simulation and technology modeling can provide solutions to the design challenges in a new class of multiprocessor array systems for multimedia.

关键词： image and video processing multimedia extensions multiprocessor arrays grain size determination technology modeling

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A proposed asynchronous object load balancing method for parallel 3D image reconstruction applications

A proposed asynchronous object load balancing method for par...

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10th international conference algorithms and architectures for parallel processing, ICA3PP 2010

作者： Alvarez-Bermejo, Jose Antonio Roca-Piera, Javier Dept of Computer Architecture and Electronics Universidad de Almería Ctra. Sacramento S/N. 04120 Spain

ISBN: (纸本)3642131182

Scientific applications usually exhibit irregular patterns of execution and high resource usage. parallel architectures are a feasible solution to face these drawbacks, but porting software to parallel platforms means the addition of an extra layer of complexity to scientific software. Abstractions such as Object Orientation and models like the concurrent object model may be of great help to develop scientific parallel applications. the shared nature of parallel architectures and the stochastic condition of parallel schedulers underline the adaptivity as a desired feature for parallel applications. Load Balancers are key for achieving adaptivity, and benefit from object oriented models in issues like load migration. In this paper we present our experiences when porting scientific software using the concurrent object abstraction and a method to asynchronously invoke load balancers. © Springer-Verlag Berlin Heidelberg 2010.

关键词： parallel architectures

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