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Using graphics processors for high performance IR query processing 09

Using graphics processors for high performance IR query proc...

引用

18th international World Wide Web conference, WWW 2009

作者： Ding, Shuai He, Jinru Yan, Hao Suel, Torsten CSE Dept. Polytechnic Inst. of NYU Brooklyn NY 11201 United States Yahoo Research Sunnyvale CA 94089 United States

ISBN: (纸本)9781605584874

Web search engines are facing formidable performance challenges due to data sizes and query loads. the major engines have to process tens of thousands of queries per second over tens of billions of documents. To deal with this heavy work-load, such engines employ massively parallel systems consisting of thousands of machines. the significant cost of operating these systems has motivated a lot of recent research into more efficient query processing mechanisms. We investigate a new way to build such high performance IR systems using graphical processing units (GPUs). GPUs were originally designed to accelerate computer graphics applications through massive on-chip parallelism. Recently a number of researchers have studied how to use GPUs for other problem domains such as databases and scientific computing [9, 8, 12]. Our contribution here is to design a basic system architecture for GPU-based high-performance IR, to develop suitable algorithms for subtasks such as inverted list compression, list intersection, and top-κ scoring, and to show how to achieve highly efficient query processing on GPU-based systems. Our experimental results for a prototype GPU-based system on 25.2 million web pages shows promising gains in query throughput. Copyright is held by the international World Wide Web conference Committee (IW3C2).

关键词： Search engines

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Adaptative resonance theory fuzzy networks parallel computation using CUDA

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10th international Work-conference on Artificial Neural Networks, IWANN 2009

作者： Martínez-Zarzuela, M. Pernas, F. J. Díaz De Pablos, A. Tejero Rodríguez, M. Antón Higuera, J. F. Díez Giralda, D. Boto Ortega, D. González Higher School of Telecommunications Engineering University of Valladolid Spain

ISBN: (纸本)3642024777

Programming of Graphics processing Units (GPUs) has evolved in a way they can be used to address and speed-up computation of algorithms exemplified by data-parallel models. In this paper parallelization of a Fuzzy ART algorithm is described and a detailed explanation of its implementation under CUDA is given. Experimental results show the algorithm runs up to 52 times faster on the GPU than on the CPU for testing and 18 times faster for training under specific conditions. © 2009 Springer Berlin Heidelberg.

关键词： Graphics processing unit

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A novel architecture of vision chip for fast traffic lane detection and FPGA implementation

A novel architecture of vision chip for fast traffic lane de...

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international conference on ASIC

作者： Yuan-Jin Li WanCheng Zhang Nan-Jian Wu State Key Laboratory for Superlattices and Microstructures Institute of Semiconductors Chinese Academy and Sciences Beijing China

this paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). the architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. the PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. the dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. the FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50 fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. the novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

关键词： Field programmable gate arrays Image processing Image edge detection Sensor arrays Reduced instruction set computing Image sensors Random access memory Alarm systems Filtering parallel algorithms

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Design of low power multimode time-shared filters

Design of low power multimode time-shared filters

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international conference on Information, Communications and Signal processing

作者： Navin Michael A.P. Vinod Christophe Moy Jacques Palicot School of Computer Engineering Nanyang Technological University Singapore Singapore School of Computer Engineering Nanyang Technological University Singapore SUPELEC/IETR Rennes France

ISBN: (纸本)9781424446568

this paper proposes a new class of time-shared filtering architectures targeted at low power multimode portable wireless applications. the proposed structures exploit the increased cycle period available in fast filter algorithm based parallel processing structures to operate at a lower supply voltage, thereby reducing the power consumption. Further power reductions are obtained due to the reduced number of multiplications in fast filter algorithms. the paper also presents a novel power consumption model for various time-shared filter architectures in a voltage scaling regime. the proposed model can be used to investigate the impact of varying the throughput, filter architecture, filter lengths, and parallelism on the power consumption.

关键词： Power filters Finite impulse response filter Energy consumption throughput Hardware Dynamic voltage scaling parallel processing Filtering algorithms Costs Capacitance

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Analog multiplier for a low-power integrated image sensor

Analog multiplier for a low-power integrated image sensor

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international conference on Mixed Design of Integrated Circuits and Systems (MIXDES)

作者： Grzegorz Blakiewicz Microelectronic Systems Gdansk University of Technology Gdansk Poland

this paper presents a new approach to an integrated low-power and low-cost image sensor design. A matrix multiplier is proposed as a better alternative to known massively parallel architectures. the circuit, although less flexible in number of possible to implement algorithms, characterizes very low power consumption and occupied chip area. the presented circuit is designed using 0.35 mum two polysilicon, three metal CMOS technology. It consumes about 8 mW of supply power and occupies 15 mm 2 including photoreceptor matrix. A similar solution based on a massively parallel architecture needs 250 mW of supply power and occupies 40 mm 2 of chip area.

关键词： Image sensors Kernel parallel architectures Energy consumption Circuits CMOS technology Photoreceptors Image processing CMOS image sensors Power supplies

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Trends of terascale computing Chips in the next ten years

Trends of terascale computing Chips in the next ten years

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international conference on ASIC

作者： Zhonghai Lu Axel Jantsch Department of Electronics Computer and Software Systems KTH Royal Institute of Technology Stockholm Sweden

Moore's law steadily continues though facing a number of challenges. this paper identifies ongoing and desirable trends to exploit the technology capacity and further Moore's law for terascale on-chip computing architectures in the next ten years. Four foreseeable trends are: from single core to many cores, from bus-based to network-based interconnect, from centralized memory to distributed memory, and from 2D integration to 3D integration. We motivate these trends and show that the number of design choices for computing chips is increasing rapidly, leading to an exploding design space with uncountable opportunities for the innovative architect. Moreover, we envision that the multi-core Network-on-Chip will become an infrastructure backbone and accumulate many other infrastructural functions such as memory, power and resource management, testing and diagnostic services.

关键词： Streaming media Computer architecture Energy consumption Concurrent computing parallel processing Circuit synthesis Sun High performance computing Time to market Process control

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Partitioned Computation to Accelerate Scalar Multiplication for Elliptic Curve Cryptosystems

Partitioned Computation to Accelerate Scalar Multiplication ...

引用

international conference on parallel and Distributed Systems (ICPADS)

作者： Keke Wu Dawei Li Huiyun Li Tingding Chen Fengqi Yu CAS Shenzhen Institute of Advanced Technology Beijing China Chinese Academy and Sciences Beijing China Institute of VLSI Design University of Zhejiang Hangzhou China CAS Shenzhen Institute of Advanced Technology Shenzhen China

the scalar multiplication is the dominant operation in Elliptic Curve Cryptosystems (ECC). It consists of a series of point additions and point doublings. A number of algorithms have been proposed to accelerate the scalar multiplication. Most of the algorithms demand high complexity which makes scalar multiplication hard to implement. In this paper, we propose an efficient algorithm for computing scalar multiplication based on partitioning scalar and propositional logic theory to address the trade-offs between speed and complexity. Our algorithm remains low complexity compared to existing accelerated scalar multiplication algorithms, whilst it is suitable for parallel processing systems.

关键词： Acceleration Elliptic curve cryptography Partitioning algorithms Logic Elliptic curves parallel architectures Security Content addressable storage Personal digital assistants Galois fields

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parallel Discrete Event Simulation of Molecular Dynamics through Event-Based Decomposition

Parallel Discrete Event Simulation of Molecular Dynamics Thr...

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international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Martin C. Herbordt Md. Ashfaquzzaman Khan Tony Dean Department of Electrical and Computer Engineering Boston University Boston MA USA

Molecular dynamics simulation based on discrete event simulation (DMD) is emerging as an alternative to time-step driven molecular dynamics (MD). DMD uses simplified discretized models, enabling simulations to be advanced by event, with a resulting performance increase of several orders of magnitude. Even so, DMD is compute bound. Moreover, unlike MD, causality issues make DMD difficult to scale. Here we present a microarchitecture-inspired parallel algorithm for DMD: speculative execution enables multithreading, while in-order commitment ensures correctness. Our initial not-yet optimized implementation obtains scalability for a multicore processor when running realistic simulation models.

关键词： Discrete event simulation Computational modeling Biological system modeling Computer simulation Computer architecture Microarchitecture parallel algorithms Multithreading Scalability Multicore processing

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A Massively parallel Approach to Affine Transformataion in Medical Image Registration

A Massively Parallel Approach to Affine Transformataion in M...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Huynh Van Luong Jong-Myon Kim University of Ulsan Ulsan KR School of Computer Engineering and Information Technology University of Ulsan Ulsan Korea

Medical image registration plays an important role in investigating disease processes and understanding normal development and ageing. An essential component in most medical registration approaches is affine transformation. the affine transformation is made up of any combination of linear transformations (rotation and scaling) followed by translation. these algorithms are generally computationally expensive. the increasing availability of parallel computers makes parallelizing these tasks an attractive option. this paper proposes a massively parallel approach for affine transformations using a representative data parallel architecture to accelerate such algorithms. the result of our parallel approach is outstanding in terms of both processing performance and energy efficiency. the proposed parallel approach achieves a three order of computational capabilities and a second order of energy efficiency of other implementations using commercial processors such as TI DSP and ARM families.

关键词： Biomedical imaging Image registration Concurrent computing Energy efficiency Diseases Aging Availability parallel architectures Acceleration Digital signal processing

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Evaluating the Jaccard-Tanimoto Index on Multi-core architectures

Evaluating the Jaccard-Tanimoto Index on Multi-core Architec...

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9th international conference on Computational Science

作者： Sachdeva, Vipin Freimuth, Douglas M. Mueller, Chris IBM Corp Future Technol Design Ctr Indianapolis IN USA IBM Watson Res Ctr Hawthorne NY USA Indiana Univ Pervas Technol Labs Bloomington IN 47405 USA Univ Informat Technol Serv Bloomington IN 47405 USA

ISBN: (纸本)9783642019692

the Jaccard/Tanimoto coefficient is an important workload, used in a large variety of problems including drug design fingerprinting, clustering analysis, similarity web searching and image segmentation. this paper evaluates the Jaccard coefficient on three platforms: the Cell Broadband Engine (TM) processor Intel (R) Xeon (R) dual-core platform and Nvidia (R) 8800 CTX GPU. In our work, we have developed a novel parallel algorithm specially suited for the Cell/B.E. architecture for all-to-all Jaccard comparisons, that minimizes DMA transfers and reuses data in the local store. We show that our implementation on Cell/B.E. outperforms the implementations on comparable Intel platforms by 6-20X with full accuracy, and from 10-50X in reduced accuracy mode, depending on the size of the data, and by more than 60X compared to Nvidia 8800 GTX. In addition to performance, we also discuss in detail our efforts to optimize our workload on these architectures and explain how avenues for optimization on each architecture are very different and vary from one architecture to another for our workload. Our work shows that the algorithms or kernels employed for the Jaccard coefficient calculation are heavily dependent on the traits of the target hardware.

关键词： Image segmentation

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