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parallel Blob Extraction Using the Multi-core Cell Processor

Parallel Blob Extraction Using the Multi-core Cell Processor

引用

11th international conference on Advanced Concepts for Intelligent Vision Systems

作者： Kumar, Praveen Palaniappan, Kannappan Mittal, Ankush Seetharaman, Guna Univ Missouri Dept Comp Sci Columbia MO 65211 USA Indian Inst Technol Dept Elect & Comp Engn Roorkee Uttar Pradesh India Air Force Res Lab Informat Directorate 13441 Rome Italy

ISBN: (纸本)9783642046964

the rapid increase in pixel density and frame rates of modern imaging sensors is accelerating the demand for fine-grained and embedded parallelization strategies to achieve real-time implementations for video analysis. the IBM Cell Broadband Engine (BE) processor has an appealing multi-core chip architecture with multiple programming models suitable for accelerating multimedia and vector processing applications. this paper describes two parallel algorithms for blob extraction in video sequences: binary morphological operations and connected components labeling (CCL), both optimized for the Cell-BE processor. Novel parallelization and explicit instruction level optimization techniques are described for fully exploiting the computational capacity of the Synergistic processing Elements (SPEs) on the Cell processor. Experimental results show significant speedups ranging from a factor of nearly 300 for binary morphology to a factor of 8 for COL in comparison to equivalent sequential implementations applied to High Definition (HD) video.

关键词： Extraction

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Analysis of adaptive algorithm to power aware design for H.264/AVC integer motion estimation engine in HDTV application

Analysis of adaptive algorithm to power aware design for H.2...

引用

international conference on ASIC

作者： Yiqing Huang Takeshi Ikenaga Information Production and Systems Waseda University Japan

In this paper, we contribute two reconfigurable integer motion estimation (IME) architectures (namely RSADT and RPPSAD) based on adaptive algorithm. Firstly, based on the pixel difference analysis, the spatial redundancy is further exploited and three subsampling patterns are selected adaptively. Secondly, in order to keep full data reuse, we propose an architecture level data organization for RSADT architecture. For RPPSAD, we apply pixel classification and memory organization to keep full data reuse. An interactive data loading scheme is proposed to reduce power dissipation. Experiments show that, with some extra hardware, our RSADT can averagely achieve 65.86% reduction in processing time; as for RPPSAD, it can save 25.4% to 39.8% power dissipation when processing typical HDTV720p sequences.

关键词： Algorithm design and analysis Adaptive algorithm Automatic voltage control Motion estimation Engines HDTV Hardware Power dissipation Pattern analysis Reconfigurable architectures

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Pedestrian detection implemented on a fixed-point parallel architecture

Pedestrian detection implemented on a fixed-point parallel a...

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IEEE international Symposium on Consumer Electronics (ISCE)

作者： Tom Wilson Michael Glatz Michael Hodlmoser Image Processing Group Visual8 Systems Vienna Austria Institute for Software Technology and Interactive Systems University of Technology Vienna Vienna Austria

this paper describes the implementation of a real-time pedestrian detector on a single instruction, multiple data (SIMD), fixed-point digital signal processor (DSP). We reformulate the Histogram of Oriented Gradients algorithm for calculation with a relatively simple instruction set architecture (ISA) and partition the image for parallel processing. Results obtained using an ISA simulator indicate a maximum frame rate above 40 fps for 1 MPixel images, with a detection accuracy comparable to a double-precision floating-point reference implementation.

关键词： parallel architectures Histograms Partitioning algorithms Signal processing algorithms parallel processing Object detection Cameras Hardware Support vector machines Support vector machine classification

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An efficient parallel instruction execution method for VLIW DSP

An efficient parallel instruction execution method for VLIW ...

引用

international conference on ASIC

作者： Mengjun Sun Zheng Shen Hu He Department of Microelectronics Peking University China Institute of Microelectronics Tsinghua University China Institute of Microelectronics Tsinghua University Beijing China

LILY is a high performance VLIW DSP processor for multimedia applications, developed by Tsinghua University. the processor classifies the instructions, and determines whether the instructions should be issued in parallel according to the order of the instructions. Under this parallelism, LILY processor is capable of saving one bit of operation code in the condition of inserting very few no operation (NOP) instructions. In addition, it is needed to design a corresponding assembler to accommodate the above new parallelism, which aids LILY to complete the highly efficient method. the evaluation results show satisfactory suitability of the processor for high performance applications, high code density, and small program code size.

关键词： VLIW Digital signal processing Computer architecture parallel processing Assembly Microelectronics Sun Helium Registers Hardware

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Design and Implementation of Configurable Extract Instructions targeted at Stream Cipher processing

Design and Implementation of Configurable Extract Instructio...

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2009 IEEE 8th international conference on ASIC(ASICON 2009)

作者： Longmei Nan,Zibin Dai,Wei Li,Xueying Zhang,Zhongxiang Chang

High-performance and flexible configurable extract instructions targeted at stream cipher processing are proposed by analyzing the structures and operating characteristics of more than forty public stream cipher algorithms in this *** extract instructions are designed to sustain four different data widths,and ten parallel extract modes are exploited by instruction level parallelism based on VLIW system *** more,the corresponding reconfigurable hardware circuit is *** configurating the hardware circuit,the extract of different data width and different parallel mode can be gained efficiently,so the circuit can be used as an important accelerated unit in special processing for stream cipher.

关键词： Stream Cipher,Extract Instruction,parallel processing,VILW,Configurable

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Design and implementation of an automatic parallelization of state space generation

Design and implementation of an automatic parallelization of...

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international conference on Reliability, Maintainability and Safety,ICRMS

作者： Xiao Zheng Hongliang Li Zuoning Chen Dong Wu Department Computer Science People''s Liberation Army Information and Engineering University Zhengzhou China Department Market R&D Jiangnan Institute of Computing Technology Wuxi China

It's hard for a user ignorant of parallel programming to resolve models by numerical analysis method in distributed environments, which normally involves state space generation (SSG) in parallel. To lower this threshold, an automatic parallelization approach based on MapReduce framework is presented in this paper. It has been implemented in a small-scale distributed environment, and its correctness and feasibility has been verified by the results of experiments carried on a series of models varying in scale.

关键词： State-space methods parallel programming Numerical models Numerical analysis Algorithm design and analysis Computer science Programmable logic arrays parallel processing Research and development Scheduling

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Automatic parallelization experiments on 16PE NOC based MPSOC

Automatic parallelization experiments on 16PE NOC based MPSO...

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international conference on ASIC

作者： G. Tian O. Hammami Ecole Nationale Superieure de Techniques Avancees Paris France

Multi-processors system on chip (MPSOC) is emerging as solutions for high performance embedded systems. Although important work have been achieved in the design and implementation of such systems the issue of parallel software design have not yet been properly evaluated for these targets. We present in this work automatic parallelization experiment results on a 16PE NOC based MPSOC which we designed and implemented on a single FPGA chip. All reported results come from actual execution and show that speed-up becomes limited beyond 8 processors in this external memory constrained environment.

关键词： Network-on-a-chip Pluto Tiles System-on-a-chip Testing parallel processing Embedded system Multiprocessing systems Production Software design

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Speedup analysis of data-parallel applications on Multi-core NoCs

Speedup analysis of data-parallel applications on Multi-core...

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international conference on ASIC

作者： Xiaowen Chen Zhonghai Lu Axel Jantsch Shuming Chen Microelectronics Institute National University of Defense Technology Changsha P.R. China Department of Electronic KTH-Royal Institute of Technology Stockholm Sweden

As more computing cores are integrated onto a single chip, the effect of network communication latency is becoming more and more significant on multi-core network-on-chips (NoCs). For data-parallel applications, we study the model of parallel speedup by including network communication latency in Amdahl's law. the speedup analysis considers the effect of network topology, network size, traffic model and computation/communication ratio. We also study the speedup efficiency. In our multi-core NoC platform, a real data-parallel application, i.e. matrix multiplication, is used to validate the analysis. Our theoretical analysis and the application results show that the speedup improvement is nonlinear and the speedup efficiency decreases as the system size is scaled up. Such analysis can be used to guide architects and programmers to improve parallel processing efficiency by reducing network latency with optimized network design and increasing computation proportion in the program.

关键词： Data analysis Network-on-a-chip Computer networks Delay Network topology Telecommunication traffic Traffic control Computational modeling Programming profession parallel processing

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An FPGA-based parallel Hardware Architecture for Real-time Face Detection using a Face Certainty Map

An FPGA-based Parallel Hardware Architecture for Real-time F...

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IEEE international conference on Application-specific Systems, architectures and Processors

作者： Seunghun Jin Dongkyun Kim thuy Tuong Nguyen Bongjin Jun Daijin Kim Jae Wook Jeon Dept. of Electrical and Computer Engineering Sungkyunkwan University Dept. of Computer Science and Engineering Postech School of Information and Computer Engineering Sungkyunkwan University

ISBN: (纸本)9781424445523

this paper presents an FPGA-based parallel hardware architecture for real-time face detection. An image pyramid with twenty depth levels is generated using the input image. For these scaled-down images, a local binary pattern transform and feature evaluation are performed in parallel by using the proposed block RAM-based window processing architecture. By sharing the feature look-up tables between two corresponding scaled-down images, we can reduce the use of routing resources by half. For prototyping and evaluation purposes, the hardware architecture was integrated into a Virtex-5 FPGA. the experimental result shows around 300 frames per second speed performance for processing standard VGA (640×480×8) images. In addition, the throughput of the implementation can be adjusted in proportion to the frame rate of the camera, by synchronizing each individual module with the pixel sampling clock.

关键词： Face detection Hardware architecture FPGA Image processing

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Impact of Loop Tiling on the Controller Logic of Acceleration Engines

Impact of Loop Tiling on the Controller Logic of Acceleratio...

引用

IEEE international conference on Application-specific Systems, architectures and Processors

作者： Hritam Dutta Jiali Zhai Frank Hannig Jurgen Teich Hardware/Software Co-Design Department of Computer Science University of Erlangen-Nuremberg Hardware/Software Co-Design Department of ComputerScience University of Erlangen-Nuremberg

ISBN: (纸本)9781424445523

High computational effort in modern signal and image processing applications often demands for special purpose accelerators in a system on chip (SoC). New high level synthesis methodologies enable the automated design of such programmable or non-programmable accelerators. Loop tiling is a widely used transformation in such methodologies for dimensioning of such accelerators in order to match inherent massive parallelism of considered algorithms with available functional units and processor elements. Innately, the applications are data-flow dominant and have almost no control flow, but the application of tiling techniques has the disadvantage of a more complex control and communication flow. In this paper, we present a methodology for the automatic generation of the control engines of such accelerators. the controller orchestrates the data transfer and computation. the effect of tiling on area, latency, and power overhead of the controller is studied in detail. It is shown that the controller has a substantial overhead of up to 50% in for different tiling and throughput parameters. the energy-delay product is also used as a metric for identifying optimal accelerator designs.

关键词： Logic Acceleration Engines Automatic control Communication system control Signal processing Image processing System-on-a-chip High level synthesis parallel processing

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