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parallel enhanced low design effort H.264/AVC fractional motion estimation engine for Super Hi-Vision application

Parallel enhanced low design effort H.264/AVC fractional mot...

引用

international conference on ASIC

作者： Yiqing Huang Takeshi Ikenaga Information Production and Systems Waseda University Japan

One super hi-vision (SHV) 4kx4k@60fps fractional motion estimation (FME) engine is proposed in this paper. Firstly, the mode reduction and edge detection techniques are adopted to filter out unpromising modes in the algorithm level. Secondly, two parallel improved schemes, called 16-pel scale processing and MB-split assignment, are given out in hardware level, which reduces design effort to only 217 MHz. Moreover, sub-sampling technique is adopted during SATD (sum-of-absolute-transformed-difference) generation, which saves 75% hardware cost. By using TSMC 0.18 um in worst work conditions (1.62 V, 125°C), our FME engine can achieve SHV 4kx4k@60fps real-time processing with 547.5 k gates hardware.

关键词： Automatic voltage control Motion estimation Engines Hardware Costs throughput Video compression Filtering Image edge detection Filters

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A compact analytical model for multi-island single electron transistors

A compact analytical model for multi-island single electron ...

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international conference on ASIC

作者： Yaqing Chi Bingcai Sui Liang Fang Hailiang Zhou Haiqing Zhong He Sun National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan China National University of Defense Technology Changsha Hunan CN

Multi-island single electron transistor (SET) has become a promising candidate for the kernel device of the logic circuit in the near future. A novel compact analytical model for multi-island SET is proposed in terms of current. the new approach is based on the orthodox theory of single electron tunnelling and steady-state master equation. the model is accurate and fast compared with SIMON, and suitable for the ASIC design of multi-island SET circuit simulation.

关键词： Analytical models Single electron transistors

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High Performance Global Illumination on Multi-core architectures

High Performance Global Illumination on Multi-core Architect...

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Euromicro conference on parallel, Distributed and Network-Based processing

作者： Emilio J. Padrón Margarita Amor Montserrat Bóo Ramón Doallo Dept. of Electronics and Systems Univ. A Coruña A Coruña Spain Dept. of Electronic and Computer Eng. Univ. Santiago de Compostela Santiago de Compostela Spain

Physically-based illumination is an essential factor for realistic rendering. In this context, hierarchical radiosity is one of the most accurate global illumination methods. One of the key features of the radiosity approach is that it obtains view-independent global illumination results. Unfortunately, global illumination has high computational and memory requirements, and hierarchical radiosity, though more efficient than other radiosity solutions, is not an exception. the progressive popularization of multiprocessor and multi-core processor systems makes the design and implementation of efficient parallel algorithms an appealing alternative in this field. In this paper we present a novel parallel radiosity method addressing the hierarchical radiosity computation on current homogeneous multi-core environments. One of the main contributions of our work is the use of different tasks to exploit the independent interactions among the geometric elements in the scene. Our parallel solution leads to a versatile radiosity implementation that takes advantage of the multiple computational resources in the system, such as multi-core processors and SMT (simultaneous multithreading) capabilities. Good results in terms of performance have been achieved.

关键词： Lighting Concurrent computing Multicore processing Layout Surface-mount technology Distributed computing Multithreading Proposals Processor scheduling Computer architecture

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A power and area efficient architecture of convolver based on ram

A power and area efficient architecture of convolver based o...

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international conference on ASIC

作者： Chen Chen Yun Chen Yuan Chen An Pan Xiao-Yang Zeng State Key Laboratory of ASIC & System Fudan University Shanghai China

this paper proposes a novel architecture of the convolver which can also be used as a correlator (depend on the order in which the input sequence are put in). It is power and area efficient compared with the typical architectures based on registers. Two groups of convolver are implemented to show the improvement. One group deals with two 12 bit data sequences of length 64, while another deals with two 12 bit data sequences of length 256, with each group containing a ram based one and a conventional one. the synthesis results by DC using SMIC 0.13 um library and the results of Prime Power shows that in the second group, the area and power of the ram based one can be reduced to 91% and only 77% of the conventional one, respectively.

关键词： Convolvers Correlators Convolution Finite impulse response filter Application specific integrated circuits Hydrogen Digital signal processing Delay Libraries Registers

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Highly-parallelized motion estimation for Scalable Video Coding

Highly-parallelized motion estimation for Scalable Video Cod...

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IEEE international conference on Image processing

作者： Marijn J.H. Loomans Cornelis J. Koeleman Peter H.N. de With VDG Security BV Radonstraat 10–14 Zoetermeer NL Eindhoven University of Technology Eindhoven NL Eindhovan University of Technology Eindhoven Netherlands CycloMedia Technology BV Waardenburg NL

In this paper, we discuss the design of a highly-parallel motion estimator for real-time Scalable Video Coding (SVC). In an SVC, motion is commonly estimated bidirectionally and over various temporal distances. Current motion estimators are optimized for frame-by-frame estimation, and such estimators are designed without serious implementation constraints. To support efficient embedded applications, we propose a Highly parallel Predictive Search (HPPS) motion estimator while preserving an accurate estimation performance. the motion estimation algorithm is optimized for processing on parallel cores and utilizes a novel recursive search strategy. this strategy is based on hierarchically increasing the temporal distance in the estimation algorithm while using the state of the previous hierarchical layer as an input. Due to the absence of local recursions in the algorithm, the proposed motion estimator has a constant computational load, regardless of video activity or temporal distance. We compared our proposed motion estimator to the well-known full search, ARPS3, 3DRS and EPZS motion estimators for the SVC case, and obtain a performance close to full search (0.2dB), while outperforming other algorithms in prediction.

关键词： Motion estimation Video coding Static VAr compensators Video codecs State estimation parallel architectures Concurrent computing Security Constraint optimization Design optimization

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Dynamic context management for coarse-grained reconfigurable array DSP architecture

Dynamic context management for coarse-grained reconfigurable...

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international conference on ASIC

作者： Yanliang Liu Peng Dai Xin'an Wang Xing Zhang Lai Wei Yan Zhou Yachun Sun Peking University Beijing Beijing CN

this paper proposes a novel technique of dynamic context management scheme for coarse-grained reconfigurable array DSP architecture, which effectively reduces the power consumption and speedup reconfigurable process. the technique permits background loading of configuration data without interrupting the regular execution, overlapping computation with reconfiguration. And stored configurations can be switched dramatically reducing reconfiguration overhead if the next configuration is present in one of the alternate contexts. the proposed technique has been verified in ReMAP (Reconfigurable Multi-media Array Processors) with the Discrete Cosine Transform (DCT) of H.264 and its performance exceed other DSP and multimedia extension architectures by 1.2x to 6.2x. ReMAP was fabricated with SMIC's 0.18¿m CMOS process mainly for multimedia applications.

关键词： Digital signal processing Runtime Hardware Energy management Computer architecture Energy consumption Discrete cosine transforms Switches Computer applications Sun

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A high power efficiency reconfigurable processor for multimedia processing

A high power efficiency reconfigurable processor for multime...

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international conference on ASIC

作者： Peng Dai Xin'an Wang Xing Zhang Qiuqi Zhao Yan Zhou Yachun Sun Key Laboratory of Integrated Microsystems Science & Engineering Applications Peking University Shenzhen China University of Peking Beijing China Shenzhen National Integrated Circuit Design Industrial Center Shenzhen China

Nowadays mobile multimedia raise the demand of higher performance, larger amounts of flexibility as well as strict energy constrains. Reconfigurable multimedia array processor (ReMAP) provides architecture with high programmable coarse-grained computational resources and flexible interconnect. To reduce the power consumption of memory access, we present an approach for computing control of the reconfigurable processor. By configuring the operation and settling down the data path of computational resources as initialization, data stream in processor accomplishing algorithm implement without access context memory frequently, which can achieve barely the same energy consumption as ASICs.

关键词： Streaming media Computer architecture Energy consumption Concurrent computing parallel processing Circuit synthesis Sun High performance computing Time to market Process control

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parallel Dense Gauss-Seidel Algorithm on Many-Core Processors

Parallel Dense Gauss-Seidel Algorithm on Many-Core Processor...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Hadrien Courtecuisse Jérémie Allard INRIA Lille Nord Europe France

the Gauss-Seidel method is very efficient for solving problems such as tightly-coupled constraints with possible redundancies. However, the underlying algorithm is inherently sequential. Previous works have exploited sparsity in the system matrix to extract parallelism. In this paper, we propose to study several parallelization schemes for fully-coupled systems, unable to be parallelized by existing methods, taking advantage of recent many-cores architectures offering fast synchronization primitives. Experimental results on both multi-core CPUs and recent GPUs show that our proposed method is able to fully exploit the available units, whereas trivial parallel algorithms often fail. this method is illustrated by an application in medical intervention planning, where it is used to solve a linear complementary problem (LCP) expressing the contacts applied to a deformable body.

关键词： Gaussian processes High performance computing parallel processing Concurrent computing Jacobian matrices Computer architecture Equations Pervasive computing Linear systems Europe

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A Massively parallel Coprocessor for Convolutional Neural Networks

A Massively Parallel Coprocessor for Convolutional Neural Ne...

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IEEE international conference on Application-specific Systems, architectures and Processors

作者： Murugan Sankaradas Venkata Jakkula Srihari Cadambi Srimat Chakradhar Igor Durdanovic Eric Cosatto Hans Peter Graf NEC Laboratories America Inc.

ISBN: (纸本)9781424445523

We present a massively parallel coprocessor for accelerating Convolutional Neural Networks (CNNs), a class of important machine learning algorithms. the coprocessor functional units, consisting of parallel 2D convolution primitives and programmable units performing sub-sampling and non-linear functions specific to CNNs, implement a "meta-operator" to which a CNN may be compiled to. the coprocessor is serviced by distributed off-chip memory banks with large data bandwidth. As a key feature, we use low precision data and further increase the effective memory bandwidth by packing multiple words in every memory operation, and leverage the algorithm's simple data access patterns to use off-chip memory as a scratchpad for intermediate data, critical for CNNs. A CNN is mapped to the coprocessor hardware primitives with instructions to transfer data between the memory and coprocessor. We have implemented a prototype of the CNN coprocessor on an off-the-shelf PCI FPGA card with a single Xilinx Virtex5 LX330T FPGA and 4 DDR2 memory banks totaling 1GB. the coprocessor prototype can process at the rate of 3.4 billion multiply accumulates per second (GMACs) for CNN forward propagation, a speed that is 31x faster than a software implementation on a 2.2GHz AMD Opteron processor. For a complete face recognition application with the CNN on the coprocessor and the rest of the image processing tasks on the host, the prototype is 6-10x faster, depending on the host-coprocessor bandwidth.

关键词： Coprocessors Neural networks Cellular neural networks Bandwidth Field programmable gate arrays Software prototyping Acceleration Machine learning algorithms Convolution Hardware

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A reconfigurable architecture specific for the butterfly computing

A reconfigurable architecture specific for the butterfly com...

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international conference on ASIC

作者： Jing Xie Kai Fan Zhigang Mao Qin Wang Chao Yang Wen Zhu Suliang Wang School of Microelectronics Shanghai Jiaotong University Shanghai China

Morphosys is a reconfigurable single instruction multiple data (SIMD) architecture mainly composing of host core processor, reconfigurable cells array, frame buffer, context memory and direct memory access (DMA) module. As a common SIMD-based coarse-grained reconfigurable architecture, each context configuration and operation is based on the whole row or column function, which may be inefficient in some applications such as butterfly computing. In this paper, an improved reconfigurable architecture is proposed specific for butterfly computing application. the main work includes interconnection network design optimization, context memory architecture redefinition with quadrant binding, DMA channel addition and some other corresponding modification in reconfigurable cell. With these improvements, the new architecture can implement typical butterfly computing with cycle count about 5.53%~18.9% less than Morphosys.

关键词： Reconfigurable architectures Computer architecture Embedded computing Embedded system Digital signal processing Concurrent computing Computer applications Design optimization High performance computing Computer aided instruction

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