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Task Scheduling on Heterogeneous Devices in parallel Pervasive Systems (P²S)

15th international conference on High Performance Computing (HiPC 2008)

作者： Tamhane, Sagar A. Kumar, Mohan Univ Texas Arlington Dept Comp Sci & Engn Arlington TX 76019 USA

ISBN: (纸本)9783540898931

parallel Pervasive Systems ((PS)-S-2) comprise an ad hoc network of pervasive devices such as cell phones, handheld computers, laptops, sensors and other devices that essentially form a parallel system. Most of the current work in pervasive computing and mobile adhoc networks exploit resources on remote devices to execute compute intensive tasks. In this paper, we present a distributed task scheduling algorithm called cluster based scheduling algorithm (CBS) for parallel processing of task grpahs in pervasive environments. We reduce the communication overhead by considering the devices to be grouped into logical clusters. CBS does not require the task scheduler device to have knowledge of all characteristics of each device in the environment. the proposed scheme allows usage of multiple task scheduling algorithms. Simulation results demonstrate time and energy efficient scheduling of tasks in heterogeneous environements.

关键词： Task scheduling parallel processing pervasive computing resource constrained devices

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Euro-Par 2008 parallel processing 2008

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丛书名： Lecture Notes in Computer Science

2008年

作者： Emilio Luque Tomas Margalef Domingo Benítez

ISBN: (数字)9783540854517

ISBN: (纸本)9783540854500

this book constitutes the refereed proceedings of the 14th international conference on parallel Computing, Euro-Par 2008, held in Las Palmas de Gran Canaria, Spain, in August 2008. the 86 revised papers presented were carefully reviewed and selected from 264 submissions. the papers are organized in topical sections on support tools and environments; performance prediction and evaluation; scheduling and load balancing; high performance architectures and compilers; parallel and distributed databases; grid and cluster computing; peer-to-peer computing; distributed systems and algorithms; parallel and distributed programming; parallel numerical algorithms; distributed and high-performance multimedia; theory and algorithms for parallel computation; and high performance networks.

关键词： parallel processing (Electronic computers) Congresses.

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Real-time feature-aware video abstraction

Real-time feature-aware video abstraction

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26th international conference on Computer Graphics

作者： Zhao, Hanli Jin, Xiaogang Shen, Jianbing Mao, Xiaoyang Feng, Jieqing Zhejiang Univ State Key Lab CAD & CG Hangzhou 310027 Peoples R China Indiana Univ Purdue Univ Indianapolis IN 46202 USA Univ Yamanashi Yamanashi Japan

this paper presents a novel feature-aware rendering system that automatically abstracts videos and images with the goal of improving the effectiveness of imagery for visual communication tasks. We integrate the bilateral grid to simplify regions of low contrast, which is faster than the separable approximation to the bilateral filter, and use a feature flow-guided anisotropic edge detection filter to enhance regions of high contrast. the edges detected in this paper are smoother, more coherent and stylistic than those of the isotropic difference-of-Gaussian filter. the presented algorithms are highly parallel, allowing a real-time performance on modern GPUs. the implementation of our approach is straightforward. Several experimental examples are given at the end of the paper to demonstrate the effectiveness of our approach.

关键词： non-photorealistic rendering visual communication real-time video processing image processing

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Fast bit gather, bit scatter and bit permutation instructions for commodity microprocessors

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JOURNAL OF SIGNAL processing SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2008年第1-2期53卷 145-169页

作者： Hilewitz, Yedidya Lee, Ruby B. Princeton Univ PALMS Dept Elect Engn Princeton NJ 08544 USA

Advanced bit manipulation operations are not efficiently supported by commodity word-oriented microprocessors. Programming tricks are typically devised to shorten the long sequence of instructions needed to emulate these complicated bit operations. As these bit manipulation operations are relevant to applications that are becoming increasingly important, we propose direct support for them in microprocessors. In particular, we propose fast bit gather (or parallel extract), bit scatter (or parallel deposit) and bit permutation instructions (including group, butterfly and inverse butterfly). We show that all these instructions can be implemented efficiently using both the fast butterfly and inverse butterfly network datapaths. Specifically, we show that parallel deposit can be mapped onto a butterfly circuit and parallel extract can be mapped onto an inverse butterfly circuit. We define static, dynamic and loop invariant versions of the instructions, with static versions utilizing a much simpler functional unit. We show how a hardware decoder can be implemented for the dynamic and loop-invariant versions to generate, dynamically, the control signals for the butterfly and inverse butterfly datapaths. the simplest functional unit we propose is smaller and faster than an ALU. We also show that these instructions yield significant speedups over a basic RISC architecture for a variety of different application kernels taken from applications domains including bioinformatics, steganography, coding, compression and random number generation.

关键词： bit manipulations permutations bit scatter bit gather parallel extract parallel deposit pack unpack microprocessors instruction set architecture ISA algorithm acceleration bioinformatics pattern matching compression steganography cryptology

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parallel high-dimensional index structure for content-based information retrieval

Parallel high-dimensional index structure for content-based ...

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international conference on Computer and Information Technology (CIT)

作者： Jaewoo Chang Ahreum Lee Department of Computer Engineering Chonbuk National University of Korea Cheongju Chungbuk South Korea

To solve dasiadimensional cursepsila problem, the cell-based filtering scheme has been proposed, but it shows a linear decrease in performance as the dimensionality is increased. In this paper, we propose a parallel high-dimensional index structure for content-based information retrieval so as to cope with the linear decrease in retrieval performance. In addition, we devise data insertion, range query and k-NN query processing algorithms which are suitable for a cluster-based parallel architecture. Finally, we show that our parallel index structure achieves good retrieval performance in proportion to the number of servers in the cluster-based architecture and it outperforms a parallel version of the VA-File when the dimensionality is over 10.

关键词： Indexes Servers Distance measurement Computer architecture Microprocessors Filtering Program processors

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Memory Locality Exploitation Strategies for FFT on the CUDA Architecture

Memory Locality Exploitation Strategies for FFT on the CUDA ...

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8th international conference on High Performance Computing for Computational Science (VECPAR 2008)

作者： Gutierrez, Eladio Romero, Sergio Trenas, Maria A. Zapata, Emilio L. Univ Malaga Dept Comp Architecture E-29071 Malaga Spain

ISBN: (纸本)9783540928584

Modern graphics processing units (CPU) are becoming more and more suitable for general purpose computing due to its growing computational power. these commodity processors follow, in general, a parallel SIMD execution model whose efficiency is subject to a right exploitation of the explicit memory hierarchy, among other factors. In this paper we analyze the implementation of the Fast Fourier Transform using the programming model of the Compute Unified Device Architecture (CUDA) recently released by NVIDIA for its new graphics platforms. Within this model we propose ail FFT implementation that takes into account memory reference locality issues that are crucial in order to achieve a high execution performance. this proposal has been experimentally tested and compared with other well known approaches such as the manufacturer's FFT library.

关键词： Graphics processing Unit (GPU) Compute Unified Device Architecture (CUDA) Fast Fourier Transform memory reference locality

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Second generation Quad-Core Intel Xeon processors bring 45 nm technology and a new level of performance to HPC applications

Second generation Quad-Core Intel Xeon processors bring 45 n...

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8th international conference on Computational Science

作者： Gepner, Pawel Fraser, David L. Kowalik, Michal F. Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9783540693833

the second generation of Quad-Core Intel(R) Xeon(R) processors was launched on November 12th 2007. In this paper we take a look at what the new 45 nm based Quad-Core Intel Xeon Processor brings to high performance computing. We compare an Intel Xeon 5300 series based system with a server utilizing his successor the Intel Xeon 5400. We measure both CPU generations operating in dual socket platforms in typical HPC benchmark scenario using some common HPC benchmarks. the results presented clearly show that the new Intel Xeon processor 5400 family provides significant performance advantage on typical HPC workloads and would therefore be seen to be an appropriate choice for many of HPC installations.

关键词： HPC multi-core processors quad-core processors parallel processing benchmarks

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New information processing methods for control in magnetically confinement nuclear fusion

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8th international conference on Fuzzy Logic and Intelligent Technologies in Nuclear Science

作者： Murari, A. Vega, J. de Arcas, G. Vagliasindi, G. Consorzio RFX Assoc EURATOM ENEA Fus Corso Stati Uniti 4 Padua Italy Assoc EURATOM CIEMAT Para Fusion Madrid 28040 Spain Univ Politecn Madrid Grp Investigac Instrumentac & Acust Appl Madrid 28031 Spain Univ Catania Dip Ingn Elect Elect & Sist I-95125 Catania Italy

ISBN: (纸本)9789812799463

thermonuclear plasmas are complex and highly non-linear physical objects and therefore, in the most advanced present day devices for the study of magnetic confinement fusion, thousands of signals have to be acquired for each experiment, in order to progress with the understanding indispensable for the final reactor. On the other hand, the resulting massive databases, more than 40 Tbytes in the case of the JET joint Undertaking, pose significant problems. In this paper, solutions to reduce the shear amount of data by different compression techniques and adaptive sampling frequency architectures are presented. As an example of methods capable of providing significant help in the data analysis and real time control, a Classification and Regression Tree software is applied to the problem of regime identification, to discriminate in an automatic way whether the plasma is in the L or H confinement mode.

关键词： Real time control

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Fast bit gather, bit scatter and bit permutation instructions for commodity microprocessors

Fast bit gather, bit scatter and bit permutation instruction...

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17th IEEE international conference on Application-Specific Systems, architectures and Processors

作者： Hilewitz, Yedidya Lee, Ruby B. Princeton Univ PALMS Dept Elect Engn Princeton NJ 08544 USA

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High-Speed parallel Architecture for Software-Based CRC

High-Speed Parallel Architecture for Software-Based CRC

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Consumer Communications and Networking conference, CCNC IEEE

作者： Youngju Do Sung-Rok Yoon Taekyu Kim Kwang Eui Pyun Sin-Chong Park School of Engineering Information and Communications University Daejeon South Korea

this paper proposes a software based parallel CRC (Cyclic Redundancy Check) algorithm called ' N-byte RCC (Repetition of Computation and Combination )''. this algorithm is the iterative process of message computation by the 'slicing-by-4' and combination through the ' zero block lookup tables '. this algorithm can parallelize the CRC calculation with any number of processors. In order to verify the performance of our algorithm, we employ two different communication architectures; the single bus architecture and the 1-star topology NoC (Network on Chip) architecture. With respect to those architectures, we explore our parallel algorithm by using TLM (Transaction Level Model). From the simulation results, we present that the proposed parallel CRC algorithm with BUS and NoC architectures reduces the processing time by 28 percent and 38 percent, respectively, compared to the 'slicing-by-8' which is the fastest algorithms among other software based algorithms. Furthermore, the 1-star NoC architecture of the parallel CRC shows higher performance than the single bus architecture regardless of the number of processors.

关键词： parallel architectures Cyclic redundancy check Computer architecture Software algorithms Iterative algorithms Network-on-a-chip Concurrent computing Table lookup Network topology parallel algorithms

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