this paper presents a hardware implementation of a secure and reliable k-out-of-n threshold based secret image sharing method. the secret image is divided into n image shares so that any k image shares are sufficient ...
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this paper presents a hardware implementation of a secure and reliable k-out-of-n threshold based secret image sharing method. the secret image is divided into n image shares so that any k image shares are sufficient to reconstruct the secret image in a lossless manner, but (k-1) or fewer image shares cannot reveal anything about the secret image. this secret sharing method comprises multiple independent computations which are conducive to parallelprocessingarchitectures. Fine-grained field programmable gate array (FPGA) architectures are the near optimal hardware platform for performing parallelprocessing. this paper illustrates the design and implementation of the secret image sharing method for 8-bit grayscale images on an FPGA which enhances execution time. On average, it was found that the FPGA executes image sharing and reconstruction approximately 300 times faster than a microprocessor operating on the same image.
In this paper algebraic two-level and multilevel preconditioning algorithms for second order elliptic boundary value problems are constructed, where the discretization is done using Rannacher-Turek non-conforming rota...
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ISBN:
(纸本)9783540788256
In this paper algebraic two-level and multilevel preconditioning algorithms for second order elliptic boundary value problems are constructed, where the discretization is done using Rannacher-Turek non-conforming rotated trilinear finite elements. An important point to make is that in this case the finite element spaces corresponding to two successive levels of mesh refinement are not nested in general. To handle this, a proper two-level basis is required to enable us to fit the general framework for the construction of two-level preconditioners for conforming finite elements and to generalize the method to the multilevel case. the proposed variants of hierarchical two-level basis are first introduced in a rather general setting. then, the involved parameters are studied and optimized. the major contribution of the paper is the derived estimates of the constant gamma in the strengthened CBS inequality which is shown to allow the efficient multilevel extension of the related two-level preconditioners. Representative numerical tests well illustrate the optimal complexity of the resulting iterative solver.
Clusters built from single-core systems are cost-effective as for the performance improvement and availability. However, the hardware constraints put limitations on the performance of single-core systems. Hence, it is...
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Clusters built from single-core systems are cost-effective as for the performance improvement and availability. However, the hardware constraints put limitations on the performance of single-core systems. Hence, it is difficult to meet withthe increasing high performance requirements of diversified applications at different levels for general purpose computing. A promising feasible solution is the novice multi-core systems which extend the parallelism to CPU level by integrating multiple processing units on a single die. this paper uses finite-difference time-domain (FDTD) algorithm as a case study, designing suitable parallel FDTD algorithms for three architectures: distributed-memory machines with single-core processors, shared-memory machines with dual-core processors, and the Cell Broadband Engine (Cell/B.E.) processor with nine heterogeneous cores. the experiment results show that the Cell/B.E. processor using 8 SPEs achieves a significant speedups of 7.05 faster than AMD single-core Opteron processor and 3.37 than AMD dual-core Opeteron processor at the processor level.
As new emerging multimedia applications demand constant bit rate improvements, it is becoming clear that H.264/AVC technology will not be able to meet these demands in spite of the 40-50% gain in bitrate over H.26X. R...
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As new emerging multimedia applications demand constant bit rate improvements, it is becoming clear that H.264/AVC technology will not be able to meet these demands in spite of the 40-50% gain in bitrate over H.26X. Recently, a novel video coding scheme based on the generalized finite automata (GFA) modeling of video sequences in the bitplane wavelet domain has been proposed to address this problem. Unfortunately, this scheme requires a computing workload that is difficult to support with software implementations capable of meeting the performance requirements of target applications. this paper applies transformation techniques on the GFA algorithm to map it to high performance architectures. these techniques are used to derive and implement an optimal 2D architecture based on specific performance parameters. Implementation experiments show that a single row of this architecture can match 1,536 to 11,627,906 quadrants per second depending on the size of the matched quadrant.
Growing bandwidth demand in the Internet requires new algorithms and architectures to provide a high degree of QoS. Further, to complicate the problem of Traffic Engineering, real time data processing requires more pr...
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Growing bandwidth demand in the Internet requires new algorithms and architectures to provide a high degree of QoS. Further, to complicate the problem of Traffic Engineering, real time data processing requires more priority than non-real time data processing. In this paper, we present an effective solution for improving QoS of audio and video packets in MPLS networks under real time traffic conditions. the contribution of this work is two fold. First, we investigate the impact of increased traffic on QoS parameters under heavy loading conditions and further we propose an efficient routing mechanism based on active networking concepts [1] to satisfy QoS requirements of audio and video packets.
In contrast to the minimization of deterministic finite antomata (DFA's), the task of constructing a minimal nondeterministic finite automaton (NFA) for a given NFA is PSPACE-complete. this fact motivates the foll...
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ISBN:
(纸本)9783540857792
In contrast to the minimization of deterministic finite antomata (DFA's), the task of constructing a minimal nondeterministic finite automaton (NFA) for a given NFA is PSPACE-complete. this fact motivates the following computational problems: (i) Find a minimal NFA for a regular language L, if L is given by another suitable formal description, resp. come up with a small NFA. (ii) Estimate the size of minimal NFA's or find at least a good approximation of their sizes. Here, we survey the known results striving to solve the problems formulated above and show that also for restricted versions of minimization of NFA's there are no efficient algorithms. Since one is unable to efficiently estimate the size of a minimal NFA in an algorithmic way, one can ask at least for developing mathematical proof methods that, help in proving good lower hounds on the size of a minimal NFA for a given regular language. We show here that even the best known methods for this purpose fail for some concrete regular languages. Finally, we give an overview of the results about, the influence of the degree of ambiguity on the size of NFA's and discuss the relation between the descriptional complexity of NFA's and NFA's with 6-transitions.
In the parameterized string matching, a given pattern P is said to match with a substring t of the text T, if there exist a bijection from the symbols of P to the symbols of t. this problem has an important applicatio...
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In the parameterized string matching, a given pattern P is said to match with a substring t of the text T, if there exist a bijection from the symbols of P to the symbols of t. this problem has an important application in software maintenance, where we wish to find the equivalency between two sections of codes. Two sections of codes are said to be equivalent, if one can be transformed into the other by renaming identifiers and variables only. Crochemore et al., 1994, has developed an algorithm (BDM) for exact string matching problem using suffix automata. Kimmo Fredriksson et al., 2006, has developed parameterized bit-parallel algorithm (parameterized shift-or) and parameterized BDM (PBDM). Parameterized shift-or (PSO) simulates finite automata in their nondeterministic form. the main drawback of PSO is: it is unable to skip text characters while matching forward. In this paper, we develop a new algorithm for parameterized string matching problem. this algorithm is based upon both suffix automata and bit parallelism concepts. this algorithm is faster than PBDM, since it processes the suffix automata in their non-deterministic form.
During vector predictive coding of digital signal series, the vector signal series, obtained by grouping adjacent samples of sources signal series, can approximate to a vector autoregressive series with stable covaria...
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ISBN:
(纸本)1424411351
During vector predictive coding of digital signal series, the vector signal series, obtained by grouping adjacent samples of sources signal series, can approximate to a vector autoregressive series with stable covariance. this paper, applying the orthogonal projection principle of Hilbert space, attempts to formulate a vector predictive coding strategy highly capable of parallelprocessing and to deduce from this strategy an adaptive parallelprocessing, algorithm, which, compared with traditional lattice algorithms, has improved remarkably in calculation complexity and storage space.
作者：
El Baz, D.CNRS
LAAS 7Ave Colonel Roche F-31077 Toulouse 4 France
the implementation of parallel asynchronous iterative algorithms on message passing architectures is considered. Several issues related to communication via message passing interfaces or libraries such as MPI-1, MPI-2...
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ISBN:
(纸本)9780769527840
the implementation of parallel asynchronous iterative algorithms on message passing architectures is considered. Several issues related to communication via message passing interfaces or libraries such as MPI-1, MPI-2, PVM or SHMEM are discussed in this survey paper Practical impleinentations are proposed.
In several digital signal processingalgorithms, computational nodes are organized in consecutive stages and data is reordered between these stages. parallel computation of such algorithms with reduced number of proce...
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ISBN:
(纸本)0769522262
In several digital signal processingalgorithms, computational nodes are organized in consecutive stages and data is reordered between these stages. parallel computation of such algorithms with reduced number of processing elements implies that several computational nodes are assigned to each element. As a drawback, permutations become more complex and require data storage. In this paper, a systematic design methodology for stride permutation networks is derived. these permutations are represented with Boolean matrices, which are decomposed and mapped directly onto register-based networks. the resulting networks are regular and scalable and they support any stride of power-of-two. In addition, the networks reach the lower bound in the number of registers indicating area-efficiency. Since the proposed methodology is systematic, it can be exploited in automated design generation.
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