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检索条件"任意字段=8th International Conference on Algorithms and Architectures for Parallel Processing"

共 2884 条记录，以下是2001-2010 订阅

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A lazy EDF interrupt scheduling algorithm for multiprocessor in parallel computing environment

A lazy EDF interrupt scheduling algorithm for multiprocessor...

引用

7th international conference on algorithms and architectures for parallel processing

作者： Liu, Peng Dai, Guojun Fu, Tingting Zeng, Hong Zhang, Xiang Hangzhou Dianzi Univ Inst Comp Applicat Technol Hangzhou 310018 Peoples R China

ISBN: (纸本)9783540729044

Many approaches have been proposed to improve efficiency of interrupt handling, most of which aim at single processor systems. Traditional model of interrupt management has been used for several decades in parallel computing environment. It can work well in most occasions, even in real-time environments. But it is often incapable to incorporate reliability and the temporal predictability demanded on hard real-time systems. Many solutions, such as In-line interrupt handling and Predictable interrupt management, all have special applying fields. In this paper we propose an algorithm that could schedule interrupts in terms of their deadlines for multiprocessor systems. Hard priorities of IRQs are still left to hardware, we only manager those who can get noticed by the kernel. Each interrupt will be scheduled only before its first execution according to their arrival time and deadlines so that it is called lazy Earliest-Deadline-First algorithm. the scheme tries to make as many as possible ISRs finish their work within the time limit. Finally we did some experiments using task simulation, which proved there was a big improvement in interrupts management.

关键词： multiprocessor interrupt scheduling parallel computing real-time system lazy EDF

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An energy efficient query processing algorithm based on relevant node selection for wireless sensor networks

An energy efficient query processing algorithm based on rele...

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8th ACIS international conference on Software Engineering, Artificial Intelligence, Networking and parallel/Distributed Computing/3rd ACIS international Workshop on Self-Assembling Wireless Networks

作者： Li, Guilin Li, Jianzhong Harbin Inst Technol Sch Comp Sci & Technol Harbin 150001 Peoples R China

ISBN: (纸本)0769529097

In this paper a novel energy efficient algorithm based on relevant node selection is proposed to deal with a new kind of approximate query, named node number constraint query, for wireless sensor networks. the query processing algorithm is composed of three parts: relevant node selection algorithm, energy efficient query dissemination and result collection algorithm. According to the user's precision request, our algorithm selects a part of nodes to answer the user's query then sends query and collects result in an energy efficient way. Simulation results show that the query processing algorithm based on relevant node selection can not only guarantee the precision of the result but also save much more energy than other algorithms.

关键词： Query processing

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Numerical simulation of a difference scheme applied in image processing based on four-order PDEs

Numerical simulation of a difference scheme applied in image...

引用

8th ACIS international conference on Software Engineering, Artificial Intelligence, Networking and parallel/Distributed Computing/3rd ACIS international Workshop on Self-Assembling Wireless Networks

作者： Zhang, Lijie Liu, Hui Wang, Yan Qingdao Technol Univ Sch Sci Shandong 266033 Peoples R China

A difference scheme for noise removal based on four-order partial differential equations is suggested. It can approximate actual image while preserving edges and avoiding blocky effects in image processing. Numerical ... 详细信息

ISBN: (纸本)0769529097

关键词： Noise abatement

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parallel Implementation of Shallow Water Model on Distributed Memory architectures 20

Parallel Implementation of Shallow Water Model on Distribute...

引用

20th international conference on parallel and Distributed Computing Systems, PDCS 2007

作者： Ganeshamoorthy, K. Silva, K.P.M.K. Ranasinghe, D.N. Wait, R. Department of Computing & Intelligent Systems University of Colombo School of Computing 35 Reid Avenue Colombo-7 Sri Lanka International Science Programme Department of Information Technology Uppsala University Uppsala Sweden

ISBN: (纸本)9781604233926

In this paper, we study the impact of memory architectures, distributed memory (DM) and virtual shared memory (VSM), in the solution of parallel numerical algorithms on a multi-processor nodes cluster. the parallel implementation of the shallow water equations to model the Tsunami effect is chosen to be the case study. Data is partitioned into sub domains, namely a four into three (4 × 3) Grid scheme and a eight into six (8×6) Grid scheme which are used for the parallel implementation of this model. We present four parallel algorithms in each Grid scheme: distributed memory without threads, distributed memory with threads, virtual shared memory without threads, and virtual shared memory with threads. these four parallel algorithms have been implemented on a high performance cluster, connected to the"Nordugrid". Experiments are realized using the Message Passing Interface (MPI) library, the C/Linda, and the Linux pthreads. Subject to available memory, the virtual shared memory version without threads performs best, but as the task is scaled up, the threaded version becomes efficient in both DM and VSM implementations. © 20th international conference on parallel and Distributed Computing Systems, PDCS 2007. All rights reserved.

关键词： Memory architecture

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Redundant parallel file transfer with anticipative recursively-adjusting scheme in data grids

Redundant parallel file transfer with anticipative recursive...

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7th international conference on algorithms and architectures for parallel processing

作者： Yang, Chao-Tung Chi, Yao-Chun Han, Tsu-Fen Hsu, Ching-Hsien Tunghai Univ High Performance Comp Lab Dept Comp Sci & Informat Engn Taichung 40704 Taiwan Chung Hua Univ Dept Comp Sci & Informat Engn Hsinchu Taiwan

ISBN: (纸本)9783540729044

the co-allocation architecture was developed to enable the parallel download of datasets/servers from selected replica servers, and the bandwidth performance is the main factor that affects the internet transfer between the client and the server. therefore, it is important to reduce the difference of finished time among replica servers, and manage changeful network performance during the term of transferring as well. In this paper, we proposed an Anticipative Recursively-Adjusting Co-Allocation scheme, to adjust the workload of each selected replica server, which handles unwarned variant network performances of the selected replica servers. the algorithm is based on the previous finished rate of assigned transfer size, to anticipate that bandwidth status on next section for adjusting the workload, and further, to reduce file transfer time in a grid environment. Our approach is usefully in unstable gird environment, which reduces the wasted idle time for waiting the slowest server and decreases file transfer completion time.

关键词： Data transfer

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PHC: A rapid parallel hierarchical cubing algorithm on high dimensional OLAP

PHC: A rapid parallel hierarchical cubing algorithm on high ...

引用

7th international conference on algorithms and architectures for parallel processing

作者： Hu, Kongfa Chen, Ling Chen, Yixin Yangzhou Univ Dept Comp Sci & Engn Yangzhou 225009 Peoples R China Washington Univ Dept Comp Sci & Engn St Louis MO 63130 USA

ISBN: (纸本)9783540729044

Data cube has been playing an essential role in OLAP (online analytical processing). ne pre-computation of data cubes is critical for improving the response time of OLAP systems. However, as the size of data cube grows, the time it takes to perform this pre-computation becomes a significant performance bottleneck. In a high dimensional OLAP, it might not be practical to build all these cuboids and their indices. In this paper, we propose a parallel hierarchical cubing algorithm, based on an extension of the previous minimal cubing approach. the algorithm has two components: decomposition of the cube space based on multiple dimension attributes, and an efficient OLAP query engine based on a prefix bitmap encoding of the indices. this method partitions the high dimensional data cube into low dimensional cube segments. Such an approach permits a significant reduction of CPU and I/O overhead for many queries by restricting the number of cube segments to be processed for both the fact table and bitmap indices. the proposed data allocation and processing model support parallel I/O and parallel processing, as well as load balancing for disks and processors. Experimental results show that the proposed parallel hierarchical cubing method is significantly more efficient than other existing cubing methods.

关键词： data cube parallel hierarchical cubing algorithm (PHC) high dimensional OLAP

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A reconfigurable processor for forward error correction

引用

20th international conference on Architecture of Computing Systems

作者： Niktash, Afshin Parizi, Hooman T. Bagherzadeh, Nader Univ Calif Irvine Henry Samueli Sch Engn 536 Engn Tower Irvine CA 92697 USA

ISBN: (纸本)9783540712671

In this paper, we introduced a reconfigurable processor optimized for implementation of Forward Error Correction (FEC) algorithms and provided the implementation results of the Viterbi and Turbo decoding algorithms. In this architecture, an array of processing elements is employed to perform the required operations in parallel. Each processing element encapsulates multiple functional units which are highly optimized for FEC algorithms. A data buffer coupled with high bandwidth interconnection network facilitates pumping the data to the array and collecting the results. A processing element controller orchestrates the operation and the data movement. Different FEC algorithms like Viterbi, Turbo, Reed-Solomon and LDPC are widely used in digital communication and could be implemented on this architecture. Unlike traditional approach to programmable FEC architectures, this architecture is instruction-level programmable which results the ultimate flexibility and programmability.

关键词： reconfigurable processor processing element forward error correction viterbi turbo

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A tristate approach based on weighted mean and backward iteration

A tristate approach based on weighted mean and backward iter...

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SNPD 2007: 8th ACIS international conference on Software Engineering, Artificial Intelligence, Networking, and parallel/Distributed Computing

作者： Yanhua, Ma Chuanjun, Liu Haiying, Sun College of Information Science and Technology Qingdao University of Science and Technology Qingdao Shandong Province China Hisense Mobil Communications Technology Corporation Qingdao Shandong Province China

ISBN: (纸本)0769529097

A tristate approach (TA) for image denoising processing is presented;the noise is aimed at the presence of pepper-and-salt noise. the newness of this method is that it develops a new route in the field of image restoration. the tristate approach algorithm focuses on the removal and restoration of the noisy speckles and avoids blurring and averaging edges and non-noise pixels in a way different from other known algorithms. Any noisy pixel is replaced by an estimated value. this value is the weighted mean of the pixels neighboring to the noisy pixel or the four iteration pixels got before it. this paper describes, analyzes and compares several methods and results of removing noise from an image. We have performed the experiments by adding Salt-and-Pepper in an original image. © 2007 IEEE.

关键词： Image processing

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Classification and existence of non-oscillatory solutions for two-dimensional neutral difference system

Classification and existence of non-oscillatory solutions fo...

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8th ACIS international conference on Software Engineering, Artificial Intelligence, Networking and parallel/Distributed Computing/3rd ACIS international Workshop on Self-Assembling Wireless Networks

作者： Du, Binbin Zhang, Guang Naval Aeronaut Engn Inst Inst Appl Math Yantai Shandong 264001 Peoples R China Tianjin Univ Commerce Sch Sci Tianjin 300134 Peoples R China

In this paper, the classification of nonoscillatory solutions for a two-dimensional neutral difference system is considered. Sufficient and/or necessary conditions of existence for those solutions will be established.

ISBN: (纸本)0769529097

关键词： parallel processing systems

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parallelization schemes for memory optimization on the cell processor: A case study of image processing algorithm 07

Parallelization schemes for memory optimization on the cell ...

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8th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '07, Held in Conjunction with the PACT 2007 conference

作者： Saidani, Tarik Piskorski, Stéphane Lacassagne, Lionel Bouaziz, Samir Institut d'Electronique Fondamentale Bât. 220 91405 Orsay France Laboratoire de Recherche en Informatique Bât. 490 91405 Orsay France

ISBN: (纸本)9781595938077

the Cell processor is a typical example of a heterogeneous multiprocessor on-chip architecture that uses several levels of parallelism to deliver high performance. Reducing the gap between peak performance and effective performance is the challenge for software tool developers and the application developers. Image processing and media applications are typical "main stream" applications. We use the Harris algorithm for detection of Points of Interest in an image as a benchmark to compare the performance of several parallel schemes on a Cell processor. the impact of the DMA controlled data transfers and the synchronizations between SPEs explains the differences between the performance of the different parallelization schemes. these results will be used to design a tool for an efficient mapping of image processing applications on multi-core architectures. Copyright 2007 ACM.

关键词： Data transfer

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