Currently, Ball Grid Array (BGA) is the mainstream technology of semiconductor package. the alignment accuracy of BGA ball mounting processing has a great impact on the rate of finished products. In order to reduce th...
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Currently, Ball Grid Array (BGA) is the mainstream technology of semiconductor package. the alignment accuracy of BGA ball mounting processing has a great impact on the rate of finished products. In order to reduce the accuracy requirement for mechanism and increase the automation level, visual servo technology is introduced to BGA ball mounting processing in this paper. Coaxial lighting is adopted to emphasize the characteristics of positioning hole, and parallelprocessing flow is designed for image capture. Image smoothing and histogram equalization technology are used in image preprocessing to clear up image noise and increase image contrast. Template matching technology is used to identify the positioning hole and calculate the coordinates of positioning hole. And the difference between the coordinates of header and substrate is used as the driving signal to achieve the automatic ***-closed-loop feedback is adopted in servo system to improve positioning accuracy. And S-shape acceleration curve reduces the impact in the movement. Based on the research on the above technology, an effective scheme for automatic orientation of BGA ball mounting processing is put forward, and it will provide the great support to the development of BGA ball mounting machine.
Significant efforts are currently being pursued by several countries and IT providers to deploy SOA (Service Oriented Architecture) designs of digital government systems that integrate or implement workflows of multip...
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ISBN:
(纸本)9781595935991
Significant efforts are currently being pursued by several countries and IT providers to deploy SOA (Service Oriented Architecture) designs of digital government systems that integrate or implement workflows of multiple software services and data sources. Unfortunately, many existing applications that can be useful in digital government are not implemented as Web Services, a fact that complicates their integration and interoperation within SOAs. To address this problem, this paper presents an approach to easily wrap text-based applications into Web Services. Compared to other application-wrapping approaches, this paper's solution exposes a simpler interface to users, completely hiding the complexities of understanding and developing Web Services. the approach is motivated by, and effective for, the important case of interactive applications, which is harder than batch-oriented applications and has not been considered by other approaches or software development environments. the paper briefly reviews a transnational digital government (TDG) project that requires interoperation and integration of independently developed geographically distributed information processing tools. the characteristics of SOAs are briefly described, along withtheir suitability for TDG systems and how they can be developed and deployed. the applications underlying the services needed for TDG are introduced and their SOA-relevant characteristics are identified. A framework is described for turning these applications into Web Services that are secure, support interactivity as needed, and do not constrain application functionality. the use of this framework and the evaluation of its benefits are described in the context of the deployment of application services needed by the TDG project.
AIAC algorithms (Asynchronous Iterations Asynchronous Communications) are a particular class of parallel iterative algorithms. their asynchronous nature makes them more efficient than their synchronous counterparts in...
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AIAC algorithms (Asynchronous Iterations Asynchronous Communications) are a particular class of parallel iterative algorithms. their asynchronous nature makes them more efficient than their synchronous counterparts in numerous cases as has already been shown in previous works. the first goal of this article is to compare several parallel programming environments in order to see if there is one of them which is best suited to efficiently implement AIAC algorithms. the main criterion for this comparison consists in the performances achieved in a global context of grid computing for two classical scientific problems. Nevertheless, we also take into account two secondary criteria which are the ease of programming and the ease of deployment. the second goal of this study is to extract from this comparison the important features that a parallel programming environment must have in order to be suited for the implementation of AIAC algorithms.
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a state-of-the-art algorithm in medical imagin...
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ISBN:
(纸本)0769526829
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a state-of-the-art algorithm in medical imaging, which falls in the class of 2D adaptive filter algorithms. In this paper we propose a semi-automatic mapping methodology for the generation of hardware accelerators for such a generic class of adaptive filtering applications in image processing. the final architecture deliver similar synthesis results as a hand-tuned design.
Embedded computing architectures can be designed to meet a variety of application specific requirements. However, optimized hardware can require compiler support to realize the potential of the hardware. this is espec...
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ISBN:
(纸本)0769526373
Embedded computing architectures can be designed to meet a variety of application specific requirements. However, optimized hardware can require compiler support to realize the potential of the hardware. this is especially true for embedded image processing systems where significant architectural variation is possible, and targeted software can change drastically based on architectural variation. this paper presents methods to compile a single high-level source given a fundamental variation in data-parallel target architectures processor granularity ranging from a single processor to a massively parallel processor array. the approach uses single PPE virtualization, which supports pixel-level data-parallel expressions that operate on a virtual one pixel per processing element (PPE) network and applies pixel-locating transformations to retarget the code into a given target PPE. Unlike mainstream parallel computing techniques, this technique can be applied to lightweight SIMD targets that do not provide global communication hardware or shared memory.
this paper describes an architecture dedicated to the real-time processing of census correlation in the context of the realization of passive stereovision sensors. Although DSP circuits have dramatically increased the...
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ISBN:
(纸本)9781424403127
this paper describes an architecture dedicated to the real-time processing of census correlation in the context of the realization of passive stereovision sensors. Although DSP circuits have dramatically increased their performances in terms of frequency (about 600 MHz today), DSP cores (several Multipliers Accumulators) and pipelines (Super Harvard architectures for example), FPGA circuits remain the best way to design massive parallelarchitectures when ultra fast algorithms computation are needed like it is the case in real time vision systems for collision avoidance.
We present the first parallel algorithm for building a Hausdorff Voronoi diagram (HVD). Our algorithm is targeted towards cluster computing architectures and computes the Hausdorff Voronoi diagram for non-crossing obj...
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ISBN:
(纸本)0769526365
We present the first parallel algorithm for building a Hausdorff Voronoi diagram (HVD). Our algorithm is targeted towards cluster computing architectures and computes the Hausdorff Voronoi diagram for non-crossing objects in time O(nlog(4)n/p)for input size n and p processors. In addition, our parallel algorithm also implies a new sequential HVD algorithm that constructs HVDs for noncrossing objects in time O(n log(4) n). this improves on previous sequential results and solves an open problem posed by Papadopoulou and Lee [18].
A wavelet-based parallel implementation is presented for image encoding on a multi-DSP system. the implementation is utilizing the discrete wavelet transform (DWT) and is realized in parallel processor architecture. T...
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ISBN:
(纸本)9780780397361
A wavelet-based parallel implementation is presented for image encoding on a multi-DSP system. the implementation is utilizing the discrete wavelet transform (DWT) and is realized in parallel processor architecture. the implementation has a very flexible architecture, which allows addition of extra slave processors (SPs) to the system whenever more computational power is needed. Performance of the implementation is measured and compared to a sequential reference implementation. Experimental results show that the parallel implementation is very efficient and overpowers the sequential counterpart considerably.
Methods to accurately measure Phase-locked loop lock time in multisite production environment has been presented and explained. the methods are applicable for testing transceiver frequency settling times, and frequenc...
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ISBN:
(纸本)9780780397361
Methods to accurately measure Phase-locked loop lock time in multisite production environment has been presented and explained. the methods are applicable for testing transceiver frequency settling times, and frequency and phase errors after settling for multiple devices under test in parallel using on board frequency mixers and RF signal generators or using RF receivers of automated testers. Inverse FFT was used to measure the PLL lock time in a case when PLL frequency error exists.
A motion panorama is an efficient and compact representation of the underlying video. However, the motion panorama construction process is computationally intensive and hence extremely time consuming. Addressing this ...
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ISBN:
(纸本)0769526373
A motion panorama is an efficient and compact representation of the underlying video. However, the motion panorama construction process is computationally intensive and hence extremely time consuming. Addressing this issue is crucial when one considers using motion panoramas in a real-time environment such as live video transmission. We present two parallelalgorithms for motion panorama construction, namely, the shared memory parallel algorithm (SMPA) that uses POSIX threads and the distributed memory parallel algorithm (DMPA) that uses MPI. the parallelalgorithms are tested on real videos. Experimental results show that the SMPA achieves linear speedup in most cases whereas the DMPA suffers from reduced efficiency when the number of processors exceeds 8.
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