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Address Generation Techniques for Conflict Free parallel Memory Accessing in FFT architectures

Address Generation Techniques for Conflict Free Parallel Mem...

引用

13th IEEE international conference on Electronics, Circuits and Systems (ICECS'2006), vol.3

作者： D. Reisis N. Vlassopoulos Electronics Laboratory National and Kapodistrian University of Athens Athens Greece

Speeding up FFT computations is critical for today's real time systems targeting signal processing and telecommunication applications. Aiming at the performance improvement and the efficiency of FFT architectures this paper presents an address generation technique which enables a b-radix processing stage to access in parallel b memory banks without conflicts and leads to increasing the speedup of the algorithm by a factor of b. the address generation can be realized in each b-radix stage by the use of look up tables of size O(b{sup}2) bits. the proposed technique is cost efficient and leads to the design of FFT architectures of high speed and high sustained throughput.

关键词： Computer architecture Discrete Fourier transforms Signal processing algorithms Energy consumption throughput Delay Clocks Concurrent computing Frequency Fast Fourier transforms

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the UCSC Kestrel Application-Unspecific Processor

The UCSC Kestrel Application-Unspecific Processor

引用

international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Richard Hughey Andrea Di Blas Department of Computer Engineering University of California Santa Cruz CA USA University of California Santa Cruz Santa Cruz CA US

the UCSC Kestrel parallel processor is part of an evolution from application-specific to specialized to application-unspecific processing. Kestrel combines an ALU, multiplier, and local memory, with systolic shared registers for seamless merging of communication and computation, and an innovative condition stack for rapid conditionals. the result has been a readily programmable and efficient co-processor for many applications. Experience with Kestrel indicates that programmable systolic processing, and its natural combination with the single instruction-multiple data (SIMD) parallel architecture, will be an effective design choice for years to come

关键词： Signal processing algorithms Sequences Costs Very large scale integration Systolic arrays Registers Bioinformatics Biology computing Algorithm design and analysis Concurrent computing

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Remote sensing information processing grid node with loose-coupling parallel structure

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6th international conference on Computational Science (ICCS 2006)

作者： Luo, Ying Xue, Yong Hu, Yincui Wu, Chaolin Cai, Guoyin Zheng, Lei Guo, Jianping Wan, Wei Zhong, Shaobo Chinese Acad Sci State Key Lab Remote Sensing Sci Inst Remote Sensing Applicat Beijing 100101 Peoples R China Beijing Normal Univ Inst Remote Sensing Applicat Chinese Acad Sci Beijing 100101 Peoples R China London Metropolitan Univ Dept Comp London N7 8DB England Chinese Acad Sci Grad Sch Beijing 100101 Peoples R China

ISBN: (纸本)3540343792

To use traditional algorithms and software packages on Grid system, traditional algorithms and software packages, in general, have to be modified. In this paper we focus on standards and methodologies for Grid platform within the context of the Remote Sensing Data processing Grid Node (RSDPGN) that implements a loose-coupling parallel structure for orchestrating traditional remote sensing algorithms and software packages on the Condor platform. We have implemented 17 remote sensing applications in one system using Web service and work-flow technology without any change to traditional codes. Some core algorithm codes are come from a remote sensing software package which we has neither resource codes nor APIs. Others come from the program codes accumulated by our group. the design and prototype implementation of RSDPGN are presented. the advantage and shortage of loose-coupling structure is analysed. through a case study of land surface temperature calculation from MODIS data, we demonstrate the way to modify software packages in details. Moreover we discuss the problems and solutions based on our experience such as system architecture, the kinds of functional modules, fast data transfer, and state monitoring.

关键词： Remote sensing

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JOINT FREQUENCY, TWO DIMENSIONAL ARRIVAL ANGLES ESTIMATIONS VIA MARKED SIGNAL SUBSPACE

JOINT FREQUENCY, TWO DIMENSIONAL ARRIVAL ANGLES ESTIMATIONS ...

引用

international conference on Signal processing Proceedings (ICSP)

作者： Weimin Jia Minli Yao Jianshe Song Xi'an Res. Inst. of High Technol.

An efficient frequency and 2-D arrival angles is essential in array signal processing. 3-D ESPRIT for joint 2-D angle and carrier frequency estimation offers an efficient way to handle the problem. Automatic pairing of the 3-D estimates is achieved via a marked subspace. this paper exploits multiple invariance matrix pencils from parallel uniform linear array to estimate a set of unknown parameters. For many frequency estimation and directions finding, all diagonal elements of invariance matrix are located on the unit circle in the complex plane. the marked subspace technique makes the set of parameter of each radiating source locate on the circle of the same radius, whereas different sources are located on different radius circle, so that several sources can automatically pair with the marker-radius. Computer simulations are shown to be in close agreement with theoretical analysis

关键词： Frequency estimation Sensor arrays Eigenvalues and eigenfunctions Signal processing algorithms Direction of arrival estimation Array signal processing Narrowband Sensor systems Two dimensional displays Parameter estimation

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A Comparative Analysis of Adaptive Middleware architectures Based on Computational Reflection and Aspect Oriented Programming to Support Mobile Computing Applications

A Comparative Analysis of Adaptive Middleware Architectures ...

引用

IFIP 19th World Computer Congress, TC-6 and 8th IFIP/IEEE conference on Mobile and Wireless Communications Networks, MWCN 2006

作者： da Costa, Celso Maciel da Strzykalski, Marcelo Silva Bernard, Guy Pontificia Universidade Católica do Rio Grande do Sul Av. Ipiranga 6681 prédio 30 bloco 4 Porto Alegre Brazil Institut National des Télécommunications Département Infonnatique Rué Charles Fourier 91000 Evry France

ISBN: (纸本)9780387346342

Mobile computing applications are required to operate in environments in which the availability for resources and services may change significantly during system operation. As a result, mobile computing applications need to be capable of adapting to these changes to offer the best possible level of service to their users. However, traditional middleware is limited in its capability of adapting to environment changes and different users requirements. Computational Reflection and Aspect Oriented Programming paradigms have been used in the design and implementation of adaptive middleware architectures. In this paper, we propose two adaptive middleware architectures, one based on reflection and other based on aspects, which can be used to develop adaptive mobile applications. the reflection based architecture is compared to an aspect oriented based architecture from a quantitative perspective. the results suggest that middleware based on Aspect Oriented Programming can be used to build mobile adaptive applications that require less processor running time and more memory space than Computational Reflection while producing code that is easier to comprehend and modify. © 2006 by international Federation for Information processing.

关键词： Mobile computing

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Configurable Computing Platforms - Promises, Promises

Configurable Computing Platforms - Promises, Promises

引用

international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Carl Ebeling Department of Computer Science and Engineering University of Washington USA

For some time now, configurable computing has been hailed as the future for application-specific architectures. the purported advantages are well-known: the increasing NRE cost of chip fab is avoided, the same platform can be used for a variety of applications, and implementations can be fixed or upgraded in the field. But in spite of many attempts to move configurable computing platforms into the mainstream, they have yet to achieve their full promise. this talk will explore the barriers that have kept configurable computing on the sidelines thus far, and suggest steps that we might take to take advantage of its full potential

关键词： Field programmable gate arrays Hardware Computer architecture Costs Signal processing algorithms Embedded computing parallel processing Programming profession Computer science Application software

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A Novel parallel processing Architecture for Deblocking Filter in H.264 Using Vertical MB Filtering Order

A Novel Parallel Processing Architecture for Deblocking Filt...

引用

international conference on Solid-State and Integrated Circuit Technology

作者： Yue-xi Zhao An-ping Jiang SOC Laboratory Department of microelectronics Peking University Beijing China

ISBN: (纸本)1424401607

An efficient parallel processing method for deblocking filter design in H.264 video coding standard is presented in this paper. In order to reduce the memory reference and make the intermediate data reused as soon as possible, an advanced filtering order is taken, and read/write operation on external memory is executed in parallel with filtering computation. Furthermore, preloading operation is taken to reduce complexity of memory structure, and vertical MB processing order is used for improving the efficiency of intermediate data reuse. As a result, the processing cycles of the proposed architecture with single-port memory architecture is reduced by 80.5% compared with the advanced architecture of previous proposals

关键词： parallel processing Filters Filtering Computer architecture Concurrent computing Read-write memory Memory architecture Proposals Automatic voltage control Decoding

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Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy

Minimum Cost for Channels and Registers in Processor Arrays ...

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international conference on Application Specific Systems (ASAP), architectures and Processors

作者： Sebastian Siegel Renate Merker Institute of Circuits and Systems Dresden University of Technology Dresden Germany

In the process of mapping compute-intensive algorithms onto arrays of processing elements (PEs) an efficient usage of channels between PEs and registers within PEs is crucial for achieving a significant algorithm acceleration. In this paper this problem is solved for algorithms represented as systems of uniform recurrence equations. We address an optimization problem in order to realize the algorithmic data dependencies within the processor array (PA) with minimum cost for channels and registers. there, we use a new mapping approach which allows a direct mapping of the algorithm onto the PA by a partitioning method. In contrast to existing approaches, we consider the issue of avoiding redundant usage of channels and registers, which can appear if one instance of a variable has to be transferred from a source PE to several sink PEs. Further, a solution of the optimization problem determines the schedule for the transfer of the variable instances in the channels and their storage in registers as well as the inner schedule for the operations in the PEs. We illustrate our method on the edge detection algorithm.

关键词： Registers Partitioning algorithms Difference equations Cost function Image edge detection parallel processing Algorithm design and analysis Circuits and systems Acceleration Topology

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parallel Testing of Phase-Locked Loop Lock Time In Production

Parallel Testing of Phase-Locked Loop Lock Time In Productio...

引用

international conference on Signal processing Proceedings (ICSP)

作者： Larry Zhang Low Power Wireless Test Group High Performance Analog Division Texas Instruments Inc. Dallas TX USA

Methods to accurately measure phase-locked loop lock time in multisite production environment has been presented and explained. the methods are applicable for testing transceiver frequency settling times, and frequency and phase errors after settling for multiple devices under test in parallel using on board frequency mixers and RF signal generators or using RF receivers of automated testers. Inverse FFT was used to measure the PLL lock time in a case when PLL frequency error exists

关键词： Phase locked loops Production Radio frequency Time measurement Frequency conversion Frequency measurement Automatic testing Transceivers Signal generators Equations

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Design and Implementation of a 64/32-bit Floating-point Division, Reciprocal, Square root, and Inverse Square root Unit

Design and Implementation of a 64/32-bit Floating-point Divi...

引用

international conference on Solid-State and Integrated Circuit Technology

作者： Chen Shuang-yan Wang Dong-hui Zhang Tie-jun Hou Chao-huan Graduate School of Chinese Academy of Sciences Beijing China Institute of Acoustics Chinese Academy and Sciences Beijing China

ISBN: (纸本)1424401607

this paper presents an efficient design and implementation of a configurable multifunctional floating-point unit for the computation of division, reciprocal, square root and inverse square root, which is fully compatible with the IEEE754 standard. Based on the Newton-Raphson method and utilizing fast parallel multipliers, the design is fast, scalable, easy to pipeline, and has very high precision. the design is implemented in Verilog, simulated in ModelSim, and then synthesized using synopsys design compiler with SMIC 0.18 micron standard cell library. Under worst condition, the critical path delay is 4.55ns

关键词： Hardware Delay Signal processing algorithms Costs Pipelines High performance computing Floating-point arithmetic Convergence Chaos Acoustics

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