In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and 70nm. these are targeted for ultra low power consumption applications. the elementary gat...
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ISBN:
(纸本)3540262083
In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and 70nm. these are targeted for ultra low power consumption applications. the elementary gates used are threshold logic gates (perceptrons). Simulations have been performed both with and without considering the delay on the wires. these simulations confirm that wires play a significant role, reducing the speed advantage of the parallel adder (over the serial one) from 4.5x to 2.2-2.4x. A promising result is that the speed of both adders improves more than 10x when migrating from 100nm to 70nm. the full adder based on threshold logic gates (used in the ripple carry adder) improves on previously known full adders, achieving 1.60 when operated at 200mV in 120nm CMOS. Finally, the speed of the parallel adder can be matched by the serial adder when operating at only 10-20% higher V-dd, while still requiring less power and energy.
the PSU/NCAR mesoscale model (known as MM5) is a limited-area, nonhydrostatic, terrain-following sigma-coordinate model designed to simulate or predict mesoscale atmospheric circulation. MM5 is popularly used in numer...
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the computing power provided by high performance low-cost PC-based Cluster and Grid platforms are attractive, and they are equal or superior to supercomputers and mainframes widely available. In this research paper, w...
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Hybrid electric vehicles (HEV) are enjoying more widespread customer acceptance than battery electric vehicles (EV) because of their performance and economy. In a parallel-type HEV, the torque assisting and battery re...
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ISBN:
(纸本)7506274078
Hybrid electric vehicles (HEV) are enjoying more widespread customer acceptance than battery electric vehicles (EV) because of their performance and economy. In a parallel-type HEV, the torque assisting and battery recharging control using the electric machine is the key point for efficient driving. this paper describes electric machine drive system based on DSP and CAN bus. the TMS320LF2407A DSP is employed to realize the functions as driving and generating (especially regeneration) function, pulse width modulation (PWM) waveforms production, signal receiving and their processing function. Control commands are transmitted to the DSP core via CAN bus. the electric machine torque command is generated from control command and its rotational speed. In the end, a PMDC of 20KW drive system based on DSP and CAN bus is used as an example. Some circuit and flow chart of controller are presented.
the low-cost and availability of network of workstations have made them attractive solution for high performance computing. Striking progress of network technology in enabling high-performance global computing, with t...
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the low-cost and availability of network of workstations have made them attractive solution for high performance computing. Striking progress of network technology in enabling high-performance global computing, withthe utilization of cluster and grid technologies, in which computational and data resources in a local or wide area network are transparently employed to solve large-scale problems. In this paper, we present implementation and design rationale of Visuel toolkit for performance measurement and analysis of parallel applications, in cluster and grid environments. Most of performance visualization tools available today for high-performance platforms show solely system performance data (e.g., CPU load, memory usage, network bandwidth, server average load), and thus, being suitable for visualisation of computing platform system activities. the Visuel toolkit, is Web-based interface designed to show performance activities of all computing nodes of a cluster or grid computing platform involved in the execution of a parallel application, such as CPU load level and memory usage of each computing node. In addition, this toolkit is able to display comparative performance data visualizations generated from a number of executions of an application under investigation, analyzing the performance of different implementations. Evaluations using this toolkit show that it outperforms in easing the process of investigation and implementation of parallel applications, in effective way.
Among visual processings in the visual networks, movement detections are carried out in the visual cortex. the visual cortex for the movement detection, consist of two layered networks, called the primary visual corte...
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ISBN:
(纸本)3540262083
Among visual processings in the visual networks, movement detections are carried out in the visual cortex. the visual cortex for the movement detection, consist of two layered networks, called the primary visual cortex (V1), followed by the middle temporal area (MT). In the biological visual neural networks, a characteristic feature is nonlinear functions, which will play important roles in the visual systems. In this paper, V1 and MT model networks, are decomposed into sub-asymmetrical networks. By the optimization of the asymmetric networks, movement detection equations are derived. then, it was clarified that asymmetric networks withthe even-odd nonlinearity combined, are fundamental in the movement detection. these facts are applied to two layered VI and MT networks, in which it was clarified that the second layer MT has an efficient ability to detect the movement.
Field Programmable Gate Arrays (FPGAs) are being used as platforms for the digital implementation of intelligent systems. Binary digital systems provide an accurate, robust, stable performance that is free from the dr...
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ISBN:
(纸本)3540262083
Field Programmable Gate Arrays (FPGAs) are being used as platforms for the digital implementation of intelligent systems. Binary digital systems provide an accurate, robust, stable performance that is free from the drift and manufacturing tolerances associated with analogue systems. However binary systems have a much lower functional density than their analogue counterparts resulting in inefficient use of silicon surface area. A design for a novel Configurable Logic Block (CLB) is presented which retains the robust qualities of digital processing whilst providing increased functional density. the circuit design uses Si/SiGe Inter-band Tunneling Diodes (ITDs) and NMOS/CMOS transistors to create quaternary memory cells in a topology and architecture suited to the implementation of neural networks. the performance of the CLB is simulated in HSPICE and the results are presented.
the recent growth of cellular phone systems, voice over IP devices, and other multimedia applications has created a considerable need for efficient voice coding algorithms. these algorithms usually require intensive a...
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the recent growth of cellular phone systems, voice over IP devices, and other multimedia applications has created a considerable need for efficient voice coding algorithms. these algorithms usually require intensive amount of signal processing capabilities and demand significant signal processing power. the current market trend of integrating multiple voice channels into a single die has further intensified the need for more powerful hardware platforms. Some new design ideas such as vocoder-specialized DSP architectures, combined RISC/DSP platforms, and adding hardware accelerators or coprocessors to the general-purpose processors have been proposed. In this paper, a new hardware accelerator design has been proposed which executes macro instructions (MIs). the proposed coprocessor can be added to each processor type that can support at least one coprocessor without modifying the compiler and redesigning the processor. It can handle computationally intensive loops in speech coding algorithmsparallel withthe main processor. the coprocessor along with software optimization reduces clock cycles required for G.723.1 by 80% and G.729 by 64% while MIPS R3000 RISC is used as the host.
We present a method for estimating the surface volume of four-dimensional objects in discrete binary images. A surface volume weight is assigned to each 2×2×2×2 configuration of image elements. the tota...
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