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检索条件"任意字段=8th International Conference on Algorithms and Architectures for Parallel Processing"

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PLX: An instruction set architecture and testbed for multimedia information processing

PLX: An instruction set architecture and testbed for multime...

引用

13th IEEE international conference on Applications-Specific Systems, architectures and Processors

作者： Lee, RB Fiskiran, AM Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

PLX is a concise instruction set architecture ( ISA) that combines the most useful features from previous generations of multimedia instruction sets with newer ISA features for high- performance, low- cost multimedia information processing. Unlike previous multimedia instruction sets, PLX is not added onto a base processor ISA, but designed from the beginning as a standalone processor architecture optimized for media processing. Its design goals are high performance multimedia processing, general- purpose programmability to support an ever- growing range of applications, simplicity for constrained environments where low power and low cost are paramount, and scalability for higher performance in less constrained multimedia systems. Another design goal of PLX is to facilitate exploration and evaluation of novel techniques in instruction set architecture, microarchitecture, arithmetic, VLSI implementations, compiler optimizations, and parallel algorithm design for new computing paradigms. Key characteristics of PLX are a fully subword- parallel architecture with novel features like wordsize scalability from 32- bit to 128- bit words, a new definition of predication, and an innovative set of subword permutation instructions. We demonstrate the use and high performance of PLX on some frequently- used code kernels selected from image, video, and graphics processing applications: discrete cosine transform, pixel padding, clip test, and median filter. Our results show that a 64- bit PLX processor achieves significant speedups over a basic 64- bit RISC processor and over IA- 32 processors with MMX and SSE multimedia extensions. Using PLX's wordsize scalability feature, PLX- 128 often provides an additional 2 x speedup over PLX- 64 in a cost- effective way. Superscalar or VLIW ( Very Long Instruction Word) PLX implementations can also add additional performance through inter-instruction, rather than intra- instruction parallelism. We also describe the PLX testbed and its soft

关键词： multimedia instruction set architecture ISA processor architecture media processing

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A low power reprogrammable parallel processing VLSI architecture for computation of B-spline based medical image processing system for fast characterization of tiny objects suspended in cellular fluid

A low power reprogrammable parallel processing VLSI architec...

引用

international conference on VLSI Design

作者： Sabyasachi Mondal Arijit De P.K. Biswas Department of Electronics and Electrical Communication Engineering Indian Institute of Technology Kharagpur West Bengal India

ISBN: (纸本)0769522645

In this paper a novel medical image processing system is discussed. the core of the system is developed using a 16-bit fixed-point parallel architecture B-spline signal processing system. the statistical measure of finite word length effect is analytically developed. A modified algorithm for the reduced hardware reprogrammable interpolator has been designed. Finally some suitable modification in the hardware is made to reduce the power consumption.

关键词： parallel processing Very large scale integration Computer architecture Concurrent computing Spline Biomedical image processing Signal processing algorithms Hardware parallel architectures Length measurement

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A model for designing and implementing parallel applications using extensible architectural skeletons

A model for designing and implementing parallel applications...

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8th international conference on parallel Computing Technologies, PaCT 2005

作者： Akon, Mohammad Mursalin Goswami, Dhrubajyoti Li, Hon Fung Department of ECE University of Waterloo Canada Department of Computer Science Concordia University Montreal Canada

With the advent of hardware technologies, high-performance parallel computers and commodity clusters are becoming affordable. However, complexity of parallel application development remains one of the major obstacles towards the mainstream adoption of parallel computing. As one of the solution techniques, researchers are actively investigating the pattern-based approaches to parallel programming. As re-usable components, patterns are intended to ease the design and development phases of a parallel applications. While using patterns, a developer supplies the application specific code-components whereas the underlying environment generates most of the code for parallelization. PAS (parallel Architectural Skeleton) is one such pattern-based parallel programming model and tool, which defines the architectural aspects of parallel computational patterns. Like many other pattern-based models and tools, the PAS model was hampered by its lack of extensibility, i.e., lacking of support for the systematic addition of new skeletons to an existing skeleton repository. Lack of extensibility significantly reduces the flexibility and hence the usability of a particular approach. SuperPAS is an extension of PAS that defines a model for systematically designing and implementing PAS skeletons by a skeleton designer. the newly implemented skeletons can subsequently be used by an application developer. SuperPAS model is realized through a Skeleton Description Language (SDL), which assists both a skeleton designer and an application developer. the paper discusses the SuperPAS model through examples that use the SDL. the paper also discusses some of the recent usability and performance studies, which demonstrate that SuperPAS is a practical and usable parallel programming model and tool. © Springer-Verlag Berlin Heidelberg 2005.

关键词： parallel processing systems

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Performance analysis of applying replica selection technology for Data Grid environments

Performance analysis of applying replica selection technolog...

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8th international conference on parallel Computing Technologies, PaCT 2005

作者： Yang, Chao-Tung Chen, Chun-Hsiang Li, Kuan-Ching Hsu, Ching-Hsien High-Performance Computing Laboratory Department of Computer Science and Information Engineering Tunghai University Taichung 40704 Taiwan Parallel and Distributed Processing Center Department of Computer Science and Information Management Providence University Taichung 43301 Taiwan Department of Computer Science and Information Engineering Chung Hua University Hsinchu 300 Taiwan

the Data Grid enables the sharing, selection, and connection of a wide variety of geographically distributed computational and storage resources for solving large-scale data intensive scientific applications. Such technology efficiently manage and transfer terabytes or even petabytes of data for data-intensive, high-performance computing applications in wide-area, distributed computing environments. Replica selection process allows an application to choose a replica from replica catalog, based on its performance and data access features. In this paper, we build a Grid environment based on three existing PC Cluster environments and perform performance analysis of data transfers using GridFTP protocol over these systems. In addition, based on experimental results, it is proposed a cost model to pick the best replica, in real and dynamic network situations. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Distributed computer systems

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Distributed and parallel Computing

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丛书名： Lecture notes in computer science.

2005年

作者： Michael Hobbs

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Unified DA-based parallel Architecture for Computing the DCT and the DST

Unified DA-based Parallel Architecture for Computing the DCT...

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international conference on Information, Communications and Signal processing

作者： P.K. Meher School of Computer Engineering Nanyang Technological University Singapore

A common computing-core representation of the discrete cosine transform and discrete sine transform is derived, and a reduced-complexity algorithm is developed for computation of the proposed common computing-core. A parallel architecture based on the principle of distributed arithmetic is designed further for computation of these transforms using the common-core algorithm. the proposed scheme not only leads to a systolic-like, fully-pipelined regular and modular hardware for computing the these transforms, but also offers significant saving of hardware over the existing structures having nearly the same computational throughput. the proposed structure is devoid of complicated input/output mapping and does not involve any complex control structure. Moreover, it does not have restriction on the transform-length, and can be utilized as a reusable core for cost-effective, high-throughput implementation of either of these transforms

关键词： parallel architectures Concurrent computing Discrete cosine transforms Discrete transforms Signal processing algorithms Distributed computing Arithmetic Computer architecture Digital signal processing Algorithm design and analysis

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An approach to execute conditional branches onto SIMD multi-context reconfigurable architectures

An approach to execute conditional branches onto SIMD multi-...

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Euromicro Symposium on Digital System Design

作者： F. Rivera M. Sanchez-Elez M. Fernandez N. Bagherzadeh Depto. de Arquitectura de Computadores y Automática Universidad Complutense de Madrid Madrid Spain Department of Electrical and Computing Engineering University of California Irvine CA USA

Reconfigurable architectures have becoming very relevant in recent years. In this paper we propose a methodology dedicated to analyze interactive applications in order to execute them in a SIMD reconfigurable architecture taking into account power/performance trade-offs. this methodology starts from a kernel description of the interactive application. Kernels are conditionally executed depending on dynamic conditions like user's input data manipulation. the volume of data involved in this kind of applications combined with user's actions occurring at unexpected times strongly impact on performance. We define an execution model to deal with conditional branches accompanied by a data prefetch scheme in order to avoid reconfigurable processing unit stalls due to operands unavailability. Experimental results satisfy time constraints of interactive applications and show a power effective solution for them.

关键词： Reconfigurable architectures Prefetching Computer architecture Kernel Field programmable gate arrays parallel processing Power engineering computing Power engineering and energy Performance analysis Manipulator dynamics

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Reduction transformations for optimization parameter selection

Reduction transformations for optimization parameter selecti...

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8th international conference on High-Performance Computing in Asia-Pacific Region, HPC Asia 2005

作者： Yonggang, Che Zhenghua, Wang Xiaomei, Li National Lab. for Parallel and Distributed Processing Changsha 410073 China

ISBN: (纸本)0769524869

Program performance optimization often involves choosing right parameters to minimize the program's runtime. Selecting optimization parameters by means of execution-driven search is guaranteed to find excellent results, for it accurately accounts for all performance components of the target platform. But the major drawback of execution-driven approach is the excessive compilation time due to thousands of runs of the original program. In this article, we propose a novel technique called program reduction transformations to reduce the cost of execution-driven optimization parameter selection. It is based on our observation to the characteristics of the scientific applications and the optimization parameter selection task. the ideal is to transform the program before it is used in execution-driven parameter selection procedure. the transformed program runs in much shorter time but preserves the parameter selection quality. this technique greatly reduces the time spent on evaluating each candidate parameter and makes execution-driven optimization parameter selection affordable. We formulate the theoretic foundation of program reduction transformation. And we find several situations where reduction transformations can be legally applied. these situations are common in scientific applications. Experiments done for two math kernels and three SPEC benchmarks show that our approach is both feasible and effective. © 2005 IEEE.

关键词： Parameter estimation

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Hardware Implementation Analysis of the MD5 Hash Algorithm

Hardware Implementation Analysis of the MD5 Hash Algorithm

引用

Annual Hawaii international conference on System Sciences (HICSS)

作者： K. Jarvinen M. Tommiska J. Skytta Signal Processing Laboratory Helsinki University of Technology Finland

Hardware implementation aspects of the MD5 hash algorithm are discussed in this paper. A general architecture for MD5 is proposed and several implementations are presented. An extensive study of effects of pipelining on delay, area requirements and throughput is performed, and finally certain architectures are recommended and compared to other published MD5 designs. the designs were implemented on a Xilinx Virtex-II XC2V4000-6 FPGA and a throughput of 586 Mbps was achieved with logic requirements of only 647 slices and 2 BlockRAMs. Methods to increase the throughput to gigabit-level were also studied and an implementation of parallel MD5 blocks achieving a throughput of over 5.8 Gbps was introduced. At least to the authors' knowledge, MD5 designs presented in this paper are the fastest published FPGA-based architectures at the time of writing.

关键词： Hardware Algorithm design and analysis Signal processing algorithms throughput Field programmable gate arrays Acceleration Table lookup Logic design Logic devices Signal design

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Optimizing collective communications on SMP clusters

Optimizing collective communications on SMP clusters

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international conference on parallel processing (ICPP)

作者： Meng-Shiou Wu R.A. Kendall K. Wright Department of Electrical and Computer Engineering Scalable Computing Laboratory U.S. DOE Iowa State University Ames IA USA Scalable Computing Laboratory Ames Laboratory U.S. DOE Iowa State University Ames IA USA Department of Computer Science Scalable Computing Laboratory Ames Laboratory U.S. DOE Iowa State University Ames IA USA

We describe a generic programming model to design collective communications on SMP clusters. the programming model utilizes shared memory for collective communications and overlapping inter-node/intra-node communications, both of which are normally platform specific approaches. Several collective communications are designed based on this model and tested on three SMP clusters of different configurations. the results show that the developed collective communications can, with proper tuning, provide significant performance improvements over existing generic implementations. For example, when broadcasting an 8 MB message our implementations outperform the vendor's MPl/spl ***/Bcast by 35% on an IBM SP system, 51% on a G4 cluster, and 63% on an Intel cluster, the latter two using MPICH's MPl/spl ***/Bcast. With all-gather operations using 8 MB messages, our implementation outperform the vendor's MPI/spl ***/Allgather by 75% on the IBM SP, 60% on the Intel cluster, and 48% on the G4 cluster.

关键词： Laboratories US Department of Energy Clustering algorithms Design optimization Computer science Communication networks Testing Broadcasting Pipelines parallel architectures

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